Research on Advanced VLSI Test for Avoiding Signal Degradation

2009 Fiscal Year Final Research Report

• Project/Area Number: 19500047
• Research Category: Grant-in-Aid for Scientific Research (C)
• Allocation Type: Single-year Grants
• Section: 一般
• Research Field: Computer system/Network
• Research Institution: Kyushu Institute of Technology
• Principal Investigator: WEN Xiaoqing Kyushu Institute of Technology, 大学院・情報工学研究院, 教授 (20250897)
• Co-Investigator(Kenkyū-buntansha): KAJIHARA Seiji 九州工業大学, 大学院・情報工学研究院, 教授 (80252592)
• Project Period (FY): 2007 – 2009
• Keywords: LSIテスト / 高信頼化

Research Abstract

This research addressed the false test issues in at-speed scan testing of LSI circuits. First, it identified the excessive switching activity in the proximity (critical area) around a long sensitized path by a test vector as the main cause of false test. Next, it proposed an accurate metric for identifying risky test vectors by taking the sensitization status of long sensitized paths, proximity information, and transition level into consideration. Furthermore, this research proposed a method for extracting redundant bits from a test set that can impact the switching activity in critical areas and devised an X-filling method for determining logic values for the redundant bits so that switching activity in critical areas is effectively reduced. As a result, an advanced false-test-avoiding scheme has been established.

Research Products

• [Journal Article] シグナルインテグリティ考慮型LSIテストを目指して (2009)
  • Author(s): 温暁青
  • Journal Title: 信頼性学会誌 Vol.31,No.7 Pages: 498-505
  • Peer Reviewed
• [Journal Article] High Launch Switching Activity Reduction in At-Speed Scan Testing using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme (2009)
  • Author(s): K. Miyase, X. Wen, H. Furukawa, Y. Yamato, S. Kajihara, P. Girard, L.-T. Wang, M. Tehranipoor
  • Journal Title: IEICE Trans. Inf. & Syst. Vol.E93-D,No.1 Pages: 2-9
  • Peer Reviewed
• [Journal Article] Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment (2009)
  • Author(s): M.-F. Wu, J.-L. Huang, X. Wen, K. Miyase
  • Journal Title: IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems Vol.28,No.11 Pages: 1767-1776
  • Peer Reviewed
• [Journal Article] Estimation of Delay Test Quality and Its Application to Test Generation (2008)
  • Author(s): S. Kajihara, S. Morishima, M. Yamamoto, X. Wen, M. Fukunaga, K. Hatayama, T. Aikyo
  • Journal Title: IPSJ Transaction of System LSI Design Methodology Vol.1 Pages: 104-115
  • Peer Reviewed
• [Journal Article] Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing (2008)
  • Author(s): X. Wen, K. Miyase, T. Suzuki, S. Kajiihara, L.-T. Wang, K.K. Saluja, K. Kinoshita
  • Journal Title: Journal of Electronic Testing: Theory and Applications, Special Issue on Low Power Testing Vol.24 Pages: 379-391
  • Peer Reviewed
• [Journal Article] Test Strategies for Low-Power Devices (2008)
  • Author(s): C.P. Ravikumar, M. Hirech, X. Wen
  • Journal Title: Journal of Low Power Electronics Vol.4
  • Peer Reviewed
• [Journal Article] A Novel ATPG Method for Capture Power Reduction During Scan Testing (2007)
  • Author(s): X. Wen, S. Kajiihara, K. Miyase, T. Suzuki, K.K. Saluja, L.-T. Wang, K. Kinoshita
  • Journal Title: IEICE Trans. Inf. & Syst. E90-D,No.9 Pages: 1398-1405
  • Peer Reviewed
• [Presentation] A Path Selection Method for Delay Test Targeting Transistor Aging (2010)
  • Author(s): M. Noda, S. Kajihara, Y. Sato, K. Miyase, X. Wen, Y. Miura
  • Organizer: Digest of First IEEE Int'l Workshop on Reliability Aware System Design and Test
  • Year and Date: 20100000
• [Presentation] On Calculation of Delay Range in Fault Simulation for Test Cubes (2009)
  • Author(s): S. Oku, S. Kajihara, K. Miyase, X. Wen, Y. Sato
  • Organizer: Proc. Int'l Symp. on VLSI Design, Automation, and Test
  • Year and Date: 20090000
• [Presentation] On Calculation of Delay Range in Fault Simulation for Test Cubes (2009)
  • Author(s): Y. Yamato, X. Wen, K. Miyase, H. Furukawa, S. Kajihara
  • Organizer: Proc. IEEE 15th Pacific Rim Int'l Symp. on Dependable Computing, Automation, and Test
  • Year and Date: 20090000
• [Presentation] CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing (2009)
  • Author(s): K. Enokimoto, X. Wen, Y. Yamato, K. Miyase, H. Sone, S. Kajihara, M. Aso, H. Furukawa
  • Organizer: Proc. IEEE Asian Test Symp.
  • Year and Date: 20090000
• [Presentation] A Novel Post-ATPG IR-Drop Reduction Scheme for At-Speed Scan Testing in Broadcast-Scan-Based Test Compression Environment (2009)
  • Author(s): K. Miyase, K. Noda, H. Ito, K. Hatayama, T. Aikyo, Y. Yamato, X. Wen, S. Kajihara
  • Organizer: Proc. IEEE/ACM Int'l Conf. on Computer Aided Design
  • Year and Date: 20090000
• [Presentation] X-Identification According to Required Distribution for Industrial Circuits (2009)
  • Author(s): I. Beppu, K. Miyase, Y. Yamato, X. Wen, S. Kajihara
  • Organizer: Proc. IEEE Workshop on RTL and High Level Testing
  • Year and Date: 20090000
• [Presentation] A Capture- Safe Test Generation Scheme for At-Speed Scan Testing (2008)
  • Author(s): X. Wen, K. Miyase, S. Kajihara, H. Furukawa, Y. Yamato, A. Takashima, K. Noda, H. Ito, K. Hatayama, T. Aikyo, K.K. Saluja
  • Organizer: Proc. IEEE European Test Symp.
  • Year and Date: 20080000
• [Presentation] Reducing Power Supply Noise in Linear-Decompressor-Based Test Data Compression Environment for At-Speed Scan Testing (2008)
  • Author(s): M. -F. Wu, J. -L. Huang, X. Wen, K. Miyase
  • Organizer: Proc. IEEE Int'l Test Conf.
  • Year and Date: 20080000
• [Presentation] GA-Based X-Filling for Reducing Launch Switching Activity in At-Speed Scan Testing (2008)
  • Author(s): Y. Yamato, X. Wen, K. Miyase, H. Furukawa, S. Kajihara
  • Organizer: Proc. IEEE Int'l Workshop on Defect Based Testing
  • Year and Date: 20080000
• [Presentation] Identification of IR-drop Hot-spots in Defective Power Distribution Network Using TDF ATPG (2008)
  • Author(s): J. Ma, J. Lee, M. Tehranipoor, X. Wen, A. Crouch
  • Organizer: Proc. IEEE Int'l Workshop on Defect Based Testing
  • Year and Date: 20080000
• [Presentation] Effective IR-Drop Reduction in At-Speed Scan Testing Using Distribution-Controlling X-Identification (2008)
  • Author(s): K. Miyase, K. Noda, H. Ito, K. Hatayama, T. Aikyo, Y. Yamato, H. Furukawa, X. Wen, S. Kajihara
  • Organizer: Proc. IEEE/ACM Int'l Conf. on Computer Aided Design
  • Year and Date: 20080000
• [Presentation] CTX: A Clock- Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing (2008)
  • Author(s): H. Furukawa, X. Wen, K. Miyase, Yuta Yamato, S. Kajihara, Patrick Girard, L. -T. Wang, M. Teharanipoor
  • Organizer: Proc. IEEE Asian Test Symp.
  • Year and Date: 20080000
• [Presentation] Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing (2007)
  • Author(s): X. Wen, K. Miyase, T. Suzuki, S. Kajihara, Y. Ohsumi, K.K. Saluja
  • Organizer: Proc. IEEE/ACM Design Automation Conf.
  • Year and Date: 20070000
• [Presentation] A Novel Scheme to Reduce Power Supply Noise for High-Quality At-Speed Scan Testing (2007)
  • Author(s): X. Wen, K. Miyase, S. Kajihara, T. Suzuki, Y. Yamato, P. Girard, Y. Ohsumi, L. -T. Wang
  • Organizer: Proc. IEEE Int'l Test Conf.
  • Year and Date: 20070000
• [Presentation] A Method for Improving the Bridging Defect Coverage of a Transition Delay Test Set (2007)
  • Author(s): K. Miyase, X. Wen, S. Kajihara, M. Haraguchi, H. Furukawa
  • Organizer: Proc. IEEE Int'l Workshop on Defect Based Testing
  • Year and Date: 20070000
• [Presentation] Estimation of Delay Test Quality and Its Application to Test Generation (2007)
  • Author(s): S. Kajihara, S. Morishima, M. Yamamoto, X. Wen, M. Fukunaga, K. Hatayama, T. Aikyo
  • Organizer: Proc. IEEE/ACM Int'l Conf. on Computer-Aided Design
  • Year and Date: 20070000
• [Book] Power-Aware Testing and Test Strategies for Low Power Devices (2009)
  • Author(s): X. Wen, S. Wang
  • Total Pages: 65-115
  • Publisher: Springer
• [Book] Advanced SOC Test Architectures-Towards Nanometer Designs (2007)
  • Author(s): P. Girard, X. Wen, N. A. Touba
  • Total Pages: 37-103
  • Publisher: Elsevier Science
• [Remarks] ホームページ等
  • URL: http://aries3a.cse.kyutech.ac.jp/
• [Patent(Industrial Property Rights)] 論理値決定方法及び論理値決定プログラム (2008)
  • Inventor(s): 宮瀬絋平, 温暁青, 梶原誠司, 大和勇太
  • Industrial Property Rights Holder: 九州工業大学
  • Industrial Property Number: 特願2008-211473
  • Filing Date: 2008-08-20
• [Patent(Industrial Property Rights)] 判別方法及びプログラム (2008)
  • Inventor(s): 呉孟帆, 黄俊郎, 温暁青, 宮瀬絋平
  • Industrial Property Rights Holder: 九州工業大学・台湾大学
  • Industrial Property Number: 特願2008-273484
  • Filing Date: 2008-10-23