2009 Fiscal Year Final Research Report
Time-Domain Analog Circuit for Nano CMOS VLSI
| Project/Area Number |
19560334
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | Gunma University |
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Principal Investigator |
KOBAYASHI Haruo Gunma University, 大学院・工学研究科, 教授 (20292625)
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| Project Period (FY) |
2007 – 2009
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| Keywords | 時間領域アナログ回路 / タイムデジタイザ回路 / デジタルPWM路 / デジタルアシストアナログ回路 / 完全デジタルPLL回路 / デジタル自己校正 / デジタル誤差補正回路 |
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| Research Abstract |
We have achieved the followings for time-domain analog circuit technology in nano CMOS VLSI:
(1) High-speed, low-power AD converter architecture using time-domain redundancy algorithm.
(2) Two novel time-to-digital converter architectures
2-1) Stochastic time-to-digital converter with self-calibration
2-2) High-resolution, low-power time-to-digital converter by improving the vernia-type architecture.
(3) High-resolution, low-power digital PMW generator architecture and its application to digitally-controlled power supply
(4) EMI reduction spread-spectrum clocking algorithm with combination of PWM and PPM (pulse position modulation) in digitally-controlled power supply.
(5) Development of all digital phase-clocked loop circuit for TV tuner application with fast frequency locking.
(6) Low-noise high-frequency waveform sampling method.These results have been transferred to industry through patents and papers.
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