Theory and Optimization of Reliable Datapath Circuits having Robustness against Delay Variation

2008 Fiscal Year Final Research Report

• Project/Area Number: 19560340
• Research Category: Grant-in-Aid for Scientific Research (C)
• Allocation Type: Single-year Grants
• Section: 一般
• Research Field: Electron device/Electronic equipment
• Research Institution: Japan Advanced Institute of Science and Technology
• Principal Investigator: KANEKO Mineo Japan Advanced Institute of Science and Technology, 情報科学研究科, 教授 (00185935)
• Project Period (FY): 2007 – 2008
• Keywords: 集積回路 / CAD / 遅延ばらつき / 高位合成 / データパス / レジスタ割当

Research Abstract

LSIの製造時ばらつき,動作時動的変動の下で,機能的に正しく動作し続ける全く新しいデータパス回路方式として,(1)変数のレジスタへの割当で決まる構造的遅延変動耐性,(2)演算回路部の最小遅延補正と遅延変動耐性を組み合わせた効率化,(3)レジスタの制御タイミング順序によって動作タイミングを補償する順序クロッキングなどを提案すると共に,それらの最適設計問題について計算量的性質,具体的解法などを明らかにしている.

Research Products

• [Journal Article] Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths (2009)
  • Author(s): Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
  • Journal Title: IEICE Transactions on Fundamentals Vol. E92-A, No. 4 Pages: 1096-1105
  • Peer Reviewed
• [Journal Article] Safe Clocking for the Setup and Hold Timing Constraints in Datapath Synthesis (2009)
  • Author(s): Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
  • Journal Title: Proceedings of ACM Great Lakes Symposium on VLSI Pages: 27-32
  • Peer Reviewed
• [Journal Article] Solvability of Simultaneous Control Step and Timing Skew Assignments in High Level Synthesis (2009)
  • Author(s): Takayuki Obata, Mineo Kaneko
  • Journal Title: Proceedings of IEEE International Symposium on Circuits and Systems Pages: 1521-1524
  • Peer Reviewed
• [Journal Article] A Conjecture on the Number of Extra Registers in Safe Clocking-Based Register Assignment (2009)
  • Author(s): Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
  • Journal Title: The 15th Workshop on Synthesis And System Integration of Mixed Information technology Pages: 131-136
  • Peer Reviewed
• [Journal Article] Safe Clocking Register Assignment in Datapath Synthesis (2008)
  • Author(s): Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
  • Journal Title: Proceedings of IEEE International Conference on Computer Design Pages: 120-127
  • Peer Reviewed
• [Journal Article] Minimizing Minimum Delay Compensations for Timing Variation-Aware Datapath Synthesis (2008)
  • Author(s): Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
  • Journal Title: Proceedings of IEEE Midwest Symposium on Circuits and Systems Pages: 97-100
  • Peer Reviewed
• [Journal Article] Concurrent Skew and Control Step Assignments in RT-Level Datapath Synthesis (2008)
  • Author(s): Takayuki Obata, Mineo Kaneko
  • Journal Title: Proceedings of IEEE International Symposium on Circuits and Systems Pages: 2018-2021
  • Peer Reviewed
• [Journal Article] Novel Register Sharing in Datapath for Structural Robustness against Delay Variation (2008)
  • Author(s): Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
  • Journal Title: IEICE Transactions on Fundamentals Vol. E91-A, No. 4 Pages: 1044-1053
  • Peer Reviewed
• [Presentation] Safe Clocking Based Datapath Synthesis for the Setup and Hold Timing Constraints (2009)
  • Author(s): Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
  • Organizer: IEICE Circuits and Systems KARUIZAWA Workshop
  • Place of Presentation: 軽井沢(発表決定)
  • Year and Date: 2009-04-20
• [Presentation] Adjustable Safe Clocking and Relevant Register Assignment in Datapath Synthesis (2009)
  • Author(s): Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
  • Organizer: IEICE Technical Report
  • Place of Presentation: 沖縄
  • Year and Date: 2009-03-11
• [Presentation] 制御のタイミングスキューおよびストールに基づくLSIチューニング (2009)
  • Author(s): 上原八弓, 金子峰雄
  • Organizer: 電子情報通信学会VLSI 設計技術研究会
  • Place of Presentation: 東京
  • Year and Date: 2009-01-29
• [Presentation] A Note on the Number of Extra Registers in Safe Clocking-Based Register Assignment (2009)
  • Author(s): Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
  • Organizer: IEICE Technical Report
  • Place of Presentation: 宮崎
  • Year and Date: 2009-01-22
• [Presentation] Delay Variability-Aware Datapath Synthesis Based on Safe Clocking for Setup and Hold Timing Constraints (2008)
  • Author(s): Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
  • Organizer: IEICE Technical Report
  • Place of Presentation: 福岡
  • Year and Date: 2008-11-17
• [Presentation] スキュー最適化を前提とするデータパス合成におけるスケジュール可能解空間の拡大 (2008)
  • Author(s): 小畑貴之, 金子峰雄
  • Organizer: 電子情報通信学会技術報告
  • Place of Presentation: 福岡
  • Year and Date: 2008-11-17
• [Presentation] スキュー最適化を前提とした実行可能な資源割り当て及び演算順序 (2008)
  • Author(s): Takayuki Obata, Mineo Kaneko
  • Organizer: IEICE Technical Report
  • Place of Presentation: 金沢
  • Year and Date: 2008-09-29
• [Presentation] Delay Variation-Aware Datapath Synthesis Based on Register Clustering (2008)
  • Author(s): Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
  • Organizer: IEICE Technical Report
  • Place of Presentation: 金沢
  • Year and Date: 2008-09-29
• [Presentation] データパス合成における順序制約付レジスタ割り当て問題の解法 (2008)
  • Author(s): 井上恵介, 金子峰雄, 岩垣剛
  • Organizer: DAシンポジウム
  • Place of Presentation: 静岡
  • Year and Date: 2008-08-26
• [Presentation] 高位合成における順序制約付レジスタ割り当て (2008)
  • Author(s): 井上恵介, 金子峰雄, 岩垣剛
  • Organizer: 電子情報通信学会VLSI設計技術研究会
  • Place of Presentation: 札幌
  • Year and Date: 2008-06-26
• [Presentation] データパス合成における最小遅延補正演算器数の最小化手法 (2008)
  • Author(s): 井上恵介, 金子峰雄, 岩垣剛
  • Organizer: 電子情報通信学会回路とシステム軽井沢ワークショップ
  • Place of Presentation: 軽井沢
  • Year and Date: 2008-04-21
• [Presentation] データパス合成における最小遅延補正演算器数の最小化手法 (2008)
  • Author(s): 井上恵介, 金子峰雄, 岩垣剛
  • Organizer: 電子情報通信学会技術報告VLSI設計技術研究会
  • Place of Presentation: 沖縄
  • Year and Date: 2008-03-05
• [Presentation] A Schedule Improvement with Skew Control in Datapath Synthesis (2007)
  • Author(s): Takayuki Obata, Mineo Kaneko
  • Organizer: 電子情報通信学会技術報告VLSI 設計技術研究会
  • Place of Presentation: 福岡
  • Year and Date: 2007-11-20
• [Presentation] Complexities and Algorithms of Minimum-Delay Compensation Problems in Datapath Synthesis (2007)
  • Author(s): Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
  • Organizer: 電子情報通信学会技術報告VLSI設計技術研究会
  • Place of Presentation: 福岡
  • Year and Date: 2007-11-20