• Search Research Projects
  • Search Researchers
  • How to Use
  1. Back to project page

2009 Fiscal Year Self-evaluation Report

Research on Efficient Quantum Circuit Design with Error Correction

Research Project

  • PDF
Project/Area Number 19700010
Research Category

Grant-in-Aid for Young Scientists (B)

Allocation TypeSingle-year Grants
Research Field Fundamental theory of informatics
Research InstitutionNara Institute of Science and Technology

Principal Investigator

YAMASHITA Shigeru  Nara Institute of Science and Technology, 情報理工学部, 教授 (30362833)

Project Period (FY) 2007 – 2010
Keywords量子計算 / 量子回路設計 / 設計検証 / エラー訂正 / LNN
Research Abstract

将来の量子計算の実現に向けて、量子回路設計は今から研究すべき大変重要な研究テーマであると考えられる。量子回路の中でも、量子オラクルと呼ばれる関数を計算する部分回路が設計の観点から重要であるため、エラーを考慮して効率的に量子オラクルに相当する回路を設計する手法の確立を目指す。

  • Research Products

    (5 results)

All 2009 2008

All Journal Article (3 results) (of which Peer Reviewed: 3 results) Presentation (2 results)

  • [Journal Article] Synthesis of quantum circuits for d-level systems by using Cosine-Sine decompositio2009

    • Author(s)
      Y. Makajima、Y. Kawano、H. Sekigaw、M. Nakanishi、S. Yamashita、Y. Nakashima
    • Journal Title

      Quantum Information and Computation Vol.9,No.5&6

      Pages: 423-443

    • Peer Reviewed
  • [Journal Article] Multi-Party Quantum Communication Complexity with Routed Messages2009

    • Author(s)
      S. Tani、M. Nakanishi、S. Yamashita
    • Journal Title

      IEICE transactions on Information and Systems Vol.E92-D,No.2

      Pages: 191-199

    • Peer Reviewed
  • [Journal Article] DDMF: An Efficient Decision Diagram Structure for Design Verification of Quantum Circuits under a Practical Restriction2008

    • Author(s)
      S. Yamashita、S. Minato、D.M. Miller
    • Journal Title

      IEICE Trans. Fundamentals Vol.E91-A

      Pages: 3793-3802

    • Peer Reviewed
  • [Presentation] Adaptive Equivalence-checking for Quantum Circuits2009

    • Author(s)
      S. Yamashita
    • Organizer
      Reed-Muller Workshop 2009
    • Place of Presentation
      てんぶす那覇
    • Year and Date
      2009-05-24
  • [Presentation] An Efficient Verification of Quantum Circuits under a Practical Restriction2008

    • Author(s)
      S. Yamashita
    • Organizer
      IEEE 8th International Conference on Computer and Information Technology
    • Place of Presentation
      University of Technology(オーストラリア)
    • Year and Date
      2008-07-08

URL: 

Published: 2011-06-18   Modified: 2016-04-21  

Information User Guide FAQ News Terms of Use Attribution of KAKENHI

Powered by NII kakenhi