2009 Fiscal Year Final Research Report
Automatic False Path Identification and Test Synthesis System Development to Avoid Overtesting
| Project/Area Number |
19700045
|
|---|
| Research Category |
Grant-in-Aid for Young Scientists (B)
|
| Allocation Type | Single-year Grants |
|---|
| Research Field |
Computer system/Network
|
|---|
| Research Institution | Waseda University |
|---|
Principal Investigator |
SHI Youhua Waseda University, IT研究機構, 講師 (70409655)
|
|---|
| Project Period (FY) |
2007 – 2009
|
| Keywords | 設計自動化 / 回路とシステム / VLSI設計技術 / 回路設計・CAD |
|---|
| Research Abstract |
The progress of design and manufacturing technology of LSIs makes it possible to realize more functional blocks into a chip with high speed and low power consumption. However it also leads to many new design challenges and one of them is the design and test technique due to the existence of false paths in the designs. Therefore in this research, a new analysis and test synthesis system was developed for the low cost design and test of next-generation LSIs, and with the use of this system novel test techniques, more specifically response compaction techniques and non-overtesting delay test methods, were developed.
|
