2D tunnel FET based on understanding of 2D hetero interface characteristics

2021 Fiscal Year Final Research Report

• Project/Area Number: 19H00755
• Research Category: Grant-in-Aid for Scientific Research (A)
• Allocation Type: Single-year Grants
• Section: 一般
• Review Section: Medium-sized Section 21:Electrical and electronic engineering and related fields
• Research Institution: The University of Tokyo
• Principal Investigator: Kosuke NAGASHIO 東京大学, 大学院工学系研究科(工学部), 教授 (20373441)
• Co-Investigator(Kenkyū-buntansha): 吾郷 浩樹 九州大学, グローバルイノベーションセンター, 教授 (10356355)
• Project Period (FY): 2019-04-01 – 2022-03-31
• Keywords: 超低消費電力 / トンネル現象 / 電界効果トランジスタ / 2次元材料

Outline of Final Research Achievements

Two-dimensional tunnel FETs (2D-TFETs) that can realize high drive current by reducing the tunnel distance to van der Waals distance as well as low power consumption have been intensively studied. In this study, we investigated high concentration N-type two-dimensional crystals aiming at complementary operation and found that SnS2 is suitable as a high-concentration N-type crystal for TFET. Furthermore, a P+MoS2/N-MoS2 heterostructure tunnel FET was fabricated with h-BN gate dielectric. Finally, we achieved SS of 51 mV / dec, which is less than the theoretical limit of 60 mV/dec of MOSFET. This result is high impact to ultra-low power consumption.

Free Research Field

半導体工学

Academic Significance and Societal Importance of the Research Achievements

IoTデバイス数は，数年後には～400億個に達すると指摘されているが，電子デバイスの超低消費電力化が普及の鍵である．本研究では，従来のSiトランジスタ動作の急峻性を表すSSにおいて理論限界値である60 mV/dec以下の51 mV/decを達成した．本成果は，低消費電力デバイスとして期待がかかる2次元トンネルFETの低消費電力動作を実証したものであり，今後の展開が大いに期待される．