2021 Fiscal Year Final Research Report
Low-power design of CMOS sensor circuits utilizing device mismatch
| Project/Area Number |
19K20233
|
|---|
| Research Category |
Grant-in-Aid for Early-Career Scientists
|
| Allocation Type | Multi-year Fund |
|---|
| Review Section |
Basic Section 60040:Computer system-related
|
|---|
| Research Institution | Kyoto University |
|---|
Principal Investigator |
|
|---|
| Project Period (FY) |
2019-04-01 – 2022-03-31
|
| Keywords | 集積回路 / 温度センサ / アナログ / ディジタル / モデリング / ばらつき |
|---|
| Outline of Final Research Achievements |
The purpose of this research to discover new circuit techniques that utilize the characteristic variation of MOS transistors. To show that transistor variation can be utilized as a valuable information source, we developed a ultra-low-power temperature sensor and a high-speed analog to digital converter (ADC). We could successfully develop a temperature sensor that does not require any fixed reference voltage for 0.8~1.2V operation. A test chip fabricated in a 65nm process demonstrates temperature sensing within -0.5/+1.4°C error over 0~100°C of temperature range. We then successfully developed and demonstrated a 4-bit flash ADC with 1GHz sampling rate operating under 1mW of power. Our ADC contains several hundreds of small-sized comparators where the on-chip calibration mechanism will select the appropriate comparators based statistical selection method. We then also shown an optimizing method to increase the performance under a fixed power budget.
|
| Free Research Field |
CMOS集積回路
|
| Academic Significance and Societal Importance of the Research Achievements |
トランジスタ特性のばらつきはアナログ回路設計にといて最大の敵として扱われていたが，本研究の成果により特性ばらつきを活用することができるようになった．その結果，微細トランジスタを用いた回路設計が可能となり，アナログ回路にも微細できることは学術的意義が大きい．ばらつきの活用に各々の素子のアナログ特性を測定せず，順序統計により完全ディジタルキャリブレーションが可能であるこを実証した．これは画期的なアイディアでばらつきを活用した新たな回路設計の理論としての展開が期待できる．また，消費電力を大幅に削減できることからあらゆる集積デバイスの長寿命化とエネルギー独立なデバイス実現の可能性をより一層高くした．
|
