Development of cryptographic hardware with concurrent error-correcting scheme

2019 Fiscal Year Final Research Report

• Project/Area Number: 19K21526
• Project/Area Number (Other): 18H06456 (2018)
• Research Category: Grant-in-Aid for Research Activity Start-up
• Allocation Type: Multi-year Fund (2019); Single-year Grants (2018)
• Review Section: 1001:Information science, computer engineering, and related fields
• Research Institution: Tohoku University
• Principal Investigator: Ueno Rei 東北大学, 電気通信研究所, 助教 (80826165)
• Project Period (FY): 2018-08-24 – 2020-03-31
• Keywords: ハードウェアセキュリティ / 暗号実装 / 情報セキュリティ / 算術演算回路 / VLSI

Outline of Final Research Achievements

I have developed a design methodology for highly efficient and reliable cryptographic hardware. Firstly, I have designed the world most efficient AES hardware based on a combination of optimization techniques such as transformation of Galois field. The designed hardware is suitable to and efficiently adoptable of concurrent error-detecting/correcting schemes with pipelining due to the structural feature of the designed hardware. Secondly, I have developed a highly reliable cryptographic key storage on the basis of physically unclonable function (PUF), which is resistant to tampering attacks. For securely storing cryptographic key and reliably reconstructing (i.e., reading) it, we developed novel error-correcting schemes based on multiple-valued encoding of PUF response, ternary von Neumann corrector, and rejection sampling. The error-correcting scheme achieves 128-bit cryptographic key storage with less hardware cost than any other conventional PUF-based one.

Free Research Field

ハードウェアセキュリティ

Academic Significance and Societal Importance of the Research Achievements

本成果は主に暗号ハードウェアおよび物理複製困難関数に基づく耐タンパー性暗号鍵ストレージの高効率化・高安全化・高信頼化に貢献している．暗号ハードウェアと暗号鍵ストレージの設計・実装コストを大幅に削減することで多くの情報システム，特にリソースの厳しいIoTシステムにおけるセキュリティ機能の導入が容易になり，本成果は安全な情報社会の実現に貢献するものと期待している．本成果は学術的にも高く評価されており，当該分野における世界最高峰の学術論文誌に複数論文が採択された他，本成果に関して招待講演も行っている．