2012 Fiscal Year Final Research Report
Research on 3D-integrated Silicon Nano LSI System
| Project/Area Number |
20360152
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | Chuo University (2011-2012)
The University of Tokyo (2008-2010) |
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Principal Investigator |
TAKEUCHI Ken 中央大学, 理工学部・電気電子情報通信工学科, 教授 (80463892)
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| Project Period (FY) |
2008 – 2012
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| Keywords | メモリ / SSD / 3次元 LSI / 電源 / 低消費電力 / フラッシュメモリ |
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| Research Abstract |
Inductor based low power circuits are developed to enhance the power efficiency up to 50% and decrease the memory power consumption by half. In addition, the ferroelectric MOS transistor based logic circuit system is developed which operates at an extreme
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