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2010 Fiscal Year Final Research Report

Design Methodology for Dynamic Reconfigurable Component Optimization

Research Project

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Project/Area Number 20500050
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeSingle-year Grants
Section一般
Research Field Computer system/Network
Research InstitutionOsaka University

Principal Investigator

TAKEUCHI Yoshinori  Osaka University, 大学院・情報科学研究科, 准教授 (70242245)

Co-Investigator(Kenkyū-buntansha) IMAI Masaharu  大阪大学, 大学院・情報科学研究科, 教授 (50126926)
SAKAMSHI Keishi  大阪大学, 大学院・情報科学研究科, 助教 (00346173)
Project Period (FY) 2008 – 2010
KeywordsVLSI設計技術 / 設計最適化 / 低消費電力
Research Abstract

This research studies a low power design methodology for dynamic reconfigurable components in wireless communication applications. In this research, low power and dynamically configurable 2-stage configurable decoder model is proposed. By using this model, several Forward Error Correction (FEC) decoders can be generated according to the specifications. Furthermore, by analysis of modulation and demodulation part of wireless communication systems, low bit error rate and low power system is shown to be realized by adjusting the sampling rate and computational precision of demodulation circuits.

  • Research Products

    (6 results)

All 2010 2009 2008

All Presentation (6 results)

  • [Presentation] Low Energy MDPC Implementation using Special Instructions on Application Domain Specific Instruction-Set Processor2010

    • Author(s)
      Yoshinori Takeuchi, Hiroki Ohsawa, Tomohiro Kondo, Hirofumi Iwato, Keishi Sakanushi, Masaharu Imai
    • Organizer
      Asia-Pacific Signal and Information Processing Association Annual Summit and Conference (APSIPA ACS 2010)
    • Place of Presentation
      Singapore,シンガポール(招待講演)
    • Year and Date
      2010-12-15
  • [Presentation] Two-stage Configurable Decoder Model for Multiple Forward Error Correction Standards2010

    • Author(s)
      谷口一徹, 小林礼貴, 坂主圭史, 武内良典, 今井正治
    • Organizer
      8th IEEE Workshop on Embedded Systems for Real-time Multimedia (ESTIMedia 2010)
    • Place of Presentation
      Scottsdale,アメリカ
    • Year and Date
      2010-10-29
  • [Presentation] Design and Evaluation of Digital Receiver for Low Power Wireless Communication2010

    • Author(s)
      Kazuki Ohya, Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
    • Organizer
      16th Workshop on Synthesis And System Integration of Mixed Information Technologies 2010 (SASIMI 2010)
    • Place of Presentation
      台北,台湾
    • Year and Date
      2010-10-19
  • [Presentation] 複数の誤り訂正符号に対応する再構成可能デコーダモデルの提案2010

    • Author(s)
      谷口一徹, 小林礼貴, 坂主圭史, 武内良典, 今井正治
    • Organizer
      情報処理学会,ETNET2010
    • Place of Presentation
      東京
    • Year and Date
      2010-03-26
  • [Presentation] 応用プログラムのプロファイル情報を用いたマルチプロセッサシステムの最適プロセッサ数の評価手法2009

    • Author(s)
      今村多一郎, 坂主圭史, 武内良典, 今井正治
    • Organizer
      電子情報通信学会2009ソサイエティ大会
    • Place of Presentation
      新潟
    • Year and Date
      2009-09-17
  • [Presentation] 小型・低消費エネルギーなリコンフィギャラブル・アーキテクチャ向けスイッチボックス構成情報削減手法2008

    • Author(s)
      谷口一徹, 小林礼貴, 坂主圭史, 武内良典, 今井正治
    • Organizer
      情報処理学会,DAシンポジウム2008
    • Place of Presentation
      浜松
    • Year and Date
      2008-08-26

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Published: 2012-01-26   Modified: 2016-04-21  

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