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2010 Fiscal Year Final Research Report

A study of LSI design method with balance security and testability

Research Project

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Project/Area Number 20700050
Research Category

Grant-in-Aid for Young Scientists (B)

Allocation TypeSingle-year Grants
Research Field Computer system/Network
Research InstitutionKyushu University

Principal Investigator

YOSHIMURA Masayoshi  Kyushu University, 大学院・システム情報科学研究院, 助教 (90452820)

Project Period (FY) 2008 – 2010
KeywordsVLSI設計技術 / 設計自動化
Research Abstract

It is difficult to balance with security and testability of LSIs.
We showed factors which destroy security of LSIs. DFT (design for testability) techniques which increase testability and do not decrease security were proposed. A LSI design method was constructed by techniques. This method is applied to three cipher LSIs. Experimental results show three cipher LSIs have security and testability.

  • Research Products

    (9 results)

All 2010 2009 2008 Other

All Presentation (8 results) Remarks (1 results)

  • [Presentation] A Comprehen sive Functional Time Expansion M odel Generation Method for Datap aths Using Controllers2010

    • Author(s)
      Toshinori Hosokawa
    • Organizer
      11th Worksh op on RTL and High Level Testing
    • Place of Presentation
      Shanghai, China.
    • Year and Date
      2010-12-06
  • [Presentation] An estimati on of encryption LSI testability ag ainst scan-based attack2010

    • Author(s)
      Masayoshi Yoshimura
    • Organizer
      An estima tion of encryption LSI testability a gainst scan-based attack
    • Place of Presentation
      Tokyo, Japan.
    • Year and Date
      2010-10-28
  • [Presentation] RSA暗号回路の安全なテスト容易化設計2009

    • Author(s)
      早川鉄平
    • Organizer
      デザインガイア2009
    • Place of Presentation
      高知市文化プラザ
    • Year and Date
      2009-12-04
  • [Presentation] スキャンベース攻撃とその防御法に対する定量的なセキュリティ評価2009

    • Author(s)
      伊藤侑磨
    • Organizer
      デザインガイア2009
    • Place of Presentation
      高知市文化プラザ
    • Year and Date
      2009-12-03
  • [Presentation] Design For Testability Methods against Scan based Attacks2008

    • Author(s)
      Masayoshi YOSHIMURA
    • Organizer
      Joint Seminar on Advanced LSI Test Technology
    • Place of Presentation
      Fukuoka, Japan.
    • Year and Date
      2008-12-01
  • [Presentation] A Test Generation Method for Datapath Circuits Using Functional Time Expansion Models2008

    • Author(s)
      Kazuya Sugiki
    • Organizer
      9th Workshop on RTL and High Level Testing
    • Place of Presentation
      Sapporo, Japan.
    • Year and Date
      2008-11-28
  • [Presentation] 暗号LSIにおけるテスタビリティとセキュリティに関する一考察2008

    • Author(s)
      伊藤侑磨
    • Organizer
      第59回FTC研究会
    • Place of Presentation
      石川県羽咋市
    • Year and Date
      2008-07-19
  • [Presentation] 機能的時間展開モデルを用いたデータパスのテスト生成法2008

    • Author(s)
      杉木一也
    • Place of Presentation
      石川県羽咋市
    • Year and Date
      2008-07-19
  • [Remarks] ホームページ等

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Published: 2012-02-13   Modified: 2016-04-21  

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