2020 Fiscal Year Annual Research Report
SiGe Channel FETs for High-Performance CMOS with Advanced High-K/SiGe Gate Stack
| Project/Area Number |
20J10380
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| Research Institution | The University of Tokyo |
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Principal Investigator |
李 宗恩 東京大学, 工学系研究科, 特別研究員(DC2)
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| Project Period (FY) |
2020-04-24 – 2022-03-31
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| Keywords | SiGe / MOS interface / high-k / interface trap states / EOT |
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| Outline of Annual Research Achievements |
1. We have demonstrated the record-low Dit and small hysteresis over a wide range of Ge contents from 13 to 63% by a combination of PMA at 450C and the optimum pre-cleaning process using TMA pre-treatment by TiN/ALD Y2O3/SiGe gate stacks
2. The record-low minimum D it with EOT down to 1nm is demonstrated among high-k/SiGe MOS interfaces with various Ge contents
3. 24% improvement in gm/Cox peak of Y2O3-based Si0.8Ge0.2 p-FinFET, compared to Si p-FinFET under the same EOT, is demonstrated
4. We have proposed a revised conductance method based on our new equivalent circuit for evaluating Dit at MFIS interfaces, and the ferroelectric responses in MFIS can effectively be subtracted by measuring that of a MFM capacitor
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| Current Status of Research Progress |
Current Status of Research Progress
2: Research has progressed on the whole more than it was originally planned.
Reason
1. The physical origins of reduction in Dit has been verified by the impacts of PMA temperature, oxidized IL, metal electrode, ALD high-k, TMA treatment and Ge contents, which is attributable to following two mechanisms:
(1) Reduction of the amount of sub-GeOx at MOS interfaces by the scavenging effect during PMA and TMA treatment
(2) Healing the distorted Ge-O bonds incorporating Y by high temperature PMA
2. A possible origin of the slow traps in the Y2O3/SiGe MOS interfaces can be oxygen-vacancy-related defects in ILs with the energy positions close to Ec and Ev, formed by incorporation of Ge-O bonds in ILs
3. The stress-induced degradation at SiGe interfaces after applying constant oxide electrical field can be suppressed by scaling of thickness of Y2O3
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| Strategy for Future Research Activity |
1. Study the time constant of electron trapping and detrapping in (Si,SiGe,Ge) MFIS interface by retention tests
2. Fabricate (Si,SiGe,Ge) p-FeFET and n-FeFET and hall devices
3. Understand the physical origins of the dependency of channel materials (Si,SiGe,Ge) on memory characteristics of FeFETs, including memory window, retention and endurance
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