Circuit Design Methodology for Design Efficiency and Low Power Consumption on Approximate Computing

2022 Fiscal Year Final Research Report

• Project/Area Number: 20K11737
• Research Category: Grant-in-Aid for Scientific Research (C)
• Allocation Type: Multi-year Fund
• Section: 一般
• Review Section: Basic Section 60040:Computer system-related
• Research Institution: The University of Aizu
• Principal Investigator: Yukihide Kohira 会津大学, コンピュータ理工学部, 上級准教授 (00549298)
• Project Period (FY): 2020-04-01 – 2023-03-31
• Keywords: 集積回路設計自動化 / 近似計算 / レイアウト設計 / 論理合成

Outline of Final Research Achievements

In this research, we focused on logic synthesis and layout design under the assumption that approximate computation is used, and developed a design automation system for integrated circuits that applies the merging of two nets (net pairs) to logic circuits in order to shorten design time and reduce power consumption. The developed method reduced the size of circuits by merging net pairs because the developed system reduced the number of gates and wires by merging net pairs. Compared to general design methods, the developed method improved the circuit performance such as the number of cells, chip area, power consumption, and operating speed.

Free Research Field

集積回路設計自動化

Academic Significance and Societal Importance of the Research Achievements

開発した手法により，回路性能の改善や設計時間の短縮を実現する集積回路の自動設計技術の向上に貢献した．なお，開発した設計支援システムは，アプリケーションを限定していないため，必ずしも高信頼・高精度での計算が要求されるわけではなく，誤差が含まれることを許容する画像処理や機械学習などのアプリケーションに対して，回路性能の改善や設計時間の短縮を実現できることが期待される．