2020 Fiscal Year Research-status Report
Development of an Ultra-Fast Statistical Signal/Power Integrity Analysis Simulator for the High-speed Digital System Design
| Project/Area Number |
20K14719
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| Research Institution | Nara Institute of Science and Technology |
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Principal Investigator |
Kim YoungWoo 奈良先端科学技術大学院大学, 先端科学技術研究科, 助教 (30862403)
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| Project Period (FY) |
2020-04-01 – 2022-03-31
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| Keywords | signal/power integrity / high-bandwidth memory / statistical approach / IEEE journal/conference |
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| Outline of Annual Research Achievements |
In the first year of the project, the principal investigator of this project have developed statistical eye-diagram estimation simulator considering non-linear power/ground noise and data-coding impacts. The proposed simulator can efficiently analyze signal/power integrity degradation. In the original proposal document, the project is divided into four steps:
(1) Statistical method development based on step-response simulation (SPICE), (2) Modeling to replace the step-response simulation, (3) Tool development combining the 1st and 2nd action items, (4) Application to actual problem solving. Currently, action item (1), (3) (except equation adoption part) are completed. Also, preliminary analysis result (action item (4)) are presented at the conference. The result of this project can provide a promising solution toward a long simulation time using conventional transient SPICE simulation and a large computational resource.
Using the developed simulator and research results, IEEE journals and one IEEE international conference paper are published and presented. Also, after publishing the journal and presentation at the conference, the principal investigator of this project became an associated editor in IEEE transactions. The project is conducted smoothly based on the proposed time-line and deliverables shown in the research proposal document.
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| Current Status of Research Progress |
Current Status of Research Progress
1: Research has progressed more than it was originally planned.
Reason
In the original proposal document, the project is divided into four steps:
(1) Statistical method development based on step-response simulation (SPICE), (2) Modeling to replace the step-response simulation, (3) Tool development combining the 1st and 2nd action items, (4) Application to actual problem solving.
Right after the adoption of the project, I've already prepared the 1st action item and published IEEE journal. As I result, I am working on analytical modeling part, which is the 2nd action item. Also, using the proposed method, I applied the proposed method to high-bandwidth memory analysis and presented at IEEE conference (item 4).
The project is progressing smoothly and expected to finish the analytical modeling part by 2021 Q3, completing all items and I will focus on paper writing.
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| Strategy for Future Research Activity |
Currently, analytical modeling part and application to the actual design/analysis remain. The modeling part of the chip-interposer-package-PCB power interconnection is almost finished and modeling of the p/n-channel MOSFET in two different region must be conducted. The modeling will be verified by comparing derived responses based on the analytical modeling and HSPICE will be compared.
After completing the modeling, the response derivation equation will be included into current GUI (developed simulator). Currently, step responses derived based on SPICE should be attached into the GUI. By completing the modeling, this part can be replaced by the analytical equation.
Using the proposed simulator, the HBM is analyzed and presented at the IEEE conference. More analysis will be published.
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| Causes of Carryover |
Due to COVID-19, travel expenses (international conference, business trip, workshop, and collaboration) could not be conducted. Also, conference fee and article publishing fee were also lowered, since they changed the format into online instead of on-site. As a result, budget could not be used. This project is mainly computational so most of the budget was allocated for article publishing fee and travel cost. In FY2021, the principle investigator (PI) would like to use the left over budget for realizing a simulation server, increasing the computational capacity (DRAM, hard-drives, additional computational devices). Also, in FY2021, the PI is planning to submit open access journal (IEEE Access) which requires about 2,000 US dolor per article to use the budget and foster the research result more widely.
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