2021 Fiscal Year Research-status Report
Development of an Ultra-Fast Statistical Signal/Power Integrity Analysis Simulator for the High-speed Digital System Design
| Project/Area Number |
20K14719
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| Research Institution | Nara Institute of Science and Technology |
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Principal Investigator |
Kim YoungWoo 奈良先端科学技術大学院大学, 先端科学技術研究科, 助教 (30862403)
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| Project Period (FY) |
2020-04-01 – 2023-03-31
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| Keywords | signal/power integrity / high-bandwidth memory / statistical approach / Interposer / Modeling |
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| Outline of Annual Research Achievements |
During the past two years of the project, the principal investigator (PI) of this project have developed a fast and accurate signal/power integrity simulator based on statistical approach and analytical modeling for the high-speed digital system design. In the original propose document, the project is divided into four steps:
(1) Statistical method development based on step-response simulation (SPICE), (2) Modeling to replace the SPICE simulation, (3) Tool development by merging the (1) and (2), and lastly, (4) Application to actual problem solving. All sub-steps are completed and verified to develop the novel SI/PI simulator. The result of this project can provide a promising solution toward the computational resources issues in the EDA of semiconductor systems. Using the developed simulator and research results, various IEEE journals and conferences and published and presented. Based on this result, the PI became an associate editor in IEEE transactions.
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| Current Status of Research Progress |
Current Status of Research Progress
1: Research has progressed more than it was originally planned.
Reason
In the original proposal document, the project is dived into four steps:
(1) Statistical method development based on step-response simulation (SPICE), (2) Modeling to replace the SPICE simulation, (3) Tool (GUI) development, (4) Application to actual problem solving.
Right after the adoption of the project, the PI has already prepared the (1) and published IEEE journals. In the second year, the PI focused on (2) and verified the modeling. By combining the (1) and (2), the novel simulator was developed. Using the simulator, various high-speed channels are designed and the results are submitted to various conferences and journals. However, due to COVID, participation of the international meeting and conferences was limited. As a result, the PI requested to allow one more year to show the result globally. One-year extension is allowed and the PI also acquired another JSPS project based on this result.
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| Strategy for Future Research Activity |
The developed simulator enables fast, accurate, and efficient analysis of the high-speed channel. Every design iteration, SI/PI analysis must be conducted. Using the developed simulator, computational issues in the EDA tools can be solved. Using the proposed simulator, our team will focus on design and analysis of various high-speed channels. Also, we will modify the tool so that it can be applicable to 3-dimentional integrated circuit with a new package architecture. This topic has been adopted by the JSPS early career scientists project (2022.04~2024.03). This project played important rule to acquire the future project which is related to semiconductor system design in the post-Moore’s law era.
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| Causes of Carryover |
Due to COVID-2019, travel expenses (international conferences, domestic trip, workshops, and collaboration) could not be conducted face-to-face. As a result, conference fee and article publishing fee were also lowered. Due to this reason, there is a left over budget amount. Since the research result is promising, the principal investigator would like to present this result to top-tier conferences. As a result, an extension of one year has been granted and we make the result more solid and submit to more conferences and journals.
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Research Products
(4 results)
