2022 Fiscal Year Annual Research Report
Development of an Ultra-Fast Statistical Signal/Power Integrity Analysis Simulator for the High-speed Digital System Design
| Project/Area Number |
20K14719
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| Research Institution | Nara Institute of Science and Technology |
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Principal Investigator |
Kim YoungWoo 奈良先端科学技術大学院大学, 先端科学技術研究科, 助教 (30862403)
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| Project Period (FY) |
2020-04-01 – 2023-03-31
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| Keywords | signal/power integrity / high-bandwidth memory / statistical approach / interposer / modeling |
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| Outline of Annual Research Achievements |
During the past two plus one (total of three years) years of the project, the principal investigator (PI) of this project have developed a fast and accurate signal/power integrity simulator based on statistical calculation/approach and analytical modeling for the high-speed digital system design. In the original project proposal, the research steps are divided into four:
(1) Statistical method development based on step-response simulation (SPICE), (2) Modeling to replace the SPICE simulation, (3) Tool development by merging the (1) and (2), and lastly, (4) Application to actual problem solving. All sub-steps are completed and verified to develop the novel SI/PI simulator. The result of this project can provide a promising solution toward the computational resources issues in the EDA of semiconductor systems. Using the developed simulator and research results, journals and conferences and published and presented. Based on this result, the PI became an associate editor in IEEE transactions.
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