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2012 Fiscal Year Final Research Report

Research on abstract modelsof FPGAs and evaluation of hardware algorithms

Research Project

  • PDF
Project/Area Number 21500016
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeSingle-year Grants
Section一般
Research Field Fundamental theory of informatics
Research InstitutionHiroshima University

Principal Investigator

NAKANO Koji  広島大学, 大学院・工学研究院, 教授 (30281075)

Co-Investigator(Kenkyū-buntansha) ITO Yasuaki  広島大学, 大学院・工学研究院, 助教 (40397964)
Project Period (FY) 2009 – 2012
KeywordsFPGA / アルゴリズム / 組込みハードウェア / ブロックRAM
Research Abstract

We have investigated various approaches for accelerating computation using FPGAs and found a new approach that we call FDFM(Few DSP blocks and Few memory blocks) approach. Recent FPGAs have a number of embedded DSP blocks and memory blocks. The FDFM approach uses few DSP blocks and few memory blocks to install a co-processor to compute complicated computations. We have shown that RSA encryption, image pattern matching, etc. can be done very fast.

  • Research Products

    (17 results)

All 2013 2012 2011 2010 2009 Other

All Journal Article (8 results) (of which Peer Reviewed: 8 results) Presentation (8 results) Remarks (1 results)

  • [Journal Article] An FPGA implementation for neural networks with the FDFM processor core approach2013

    • Author(s)
      Yuki Ago, Yasuaki Ito, Koji Nakano
    • Journal Title

      International Journal of Parallel, Emergent and Distributed Systems, to appear

    • Peer Reviewed
  • [Journal Article] The Parallel FDFM Processor Core Approach for CRT-based RSA Decryption2012

    • Author(s)
      Yasuaki Ito, Koji Nakano and Song Bo
    • Journal Title

      International Journal of Networking and Computing

      Volume: Vol. 2, No. 1 Pages: 79-96

    • URL

      http://www.ijnc.org/

    • Peer Reviewed
  • [Journal Article] An Algorithm to Obtain Circuits with Synchronous RAMs2012

    • Author(s)
      Md. Nazrul Islam Mondal, Koji Nakano and Yasuaki Ito
    • Journal Title

      Journal of Communication and Computer

      Volume: Volume 9, Number 5 Pages: 547-559

    • URL

      http://www.davidpublishing.com/

    • Peer Reviewed
  • [Journal Article] A Rewriting Approach to Replace Asynchronous ROMs with Synchronous Ones for the Circuits with Cycles2012

    • Author(s)
      Md. Nazrul Islam Mondal, Koji Nakano, Yasuaki Ito
    • Journal Title

      International Journal of Networking and Computing

      Volume: Vol. 2, No. 2 Pages: 269-290

    • URL

      http://www.ijnc.org/

    • Peer Reviewed
  • [Journal Article] Efficient Exhaustive Verification of the Collatz Conjecture using DSP blocks of Xilinx FPGAs2011

    • Author(s)
      Yasuaki Ito, Koji Nakano
    • Journal Title

      International Journal of Networking and Computing

      Volume: Vol. 1, No.1 Pages: 49-62

    • URL

      http://www.ijnc.org

    • Peer Reviewed
  • [Journal Article] An RSA Encryption Hardware Algorithm using a Single DSP Block and a Single Block RAM on the FPGA2011

    • Author(s)
      Song Bo, Kensuke Kawakami, Koji Nakano, Yasuaki Ito
    • Journal Title

      International Journal of Networking and Computing

      Volume: Vol. 1, No.2 Pages: 277-289

    • URL

      http://www.ijnc.org/

    • Peer Reviewed
  • [Journal Article] A Graph Rewriting Approach for Converting Asynchronous ROMs into Synchronous Ones2011

    • Author(s)
      Md. Nazrul Islam Mondal, Koji Nakano, Yasuaki Ito
    • Journal Title

      IEICE TRANSACTIONS on Information and Systems

      Volume: Vol.E94-D No.12 Pages: 2378-2388

    • URL

      http://dx.DOI:.org/10.1587/transinf.E94.D.2378

    • Peer Reviewed
  • [Journal Article] Low-latency Connected Component Labeling Using an FPGA2010

    • Author(s)
      Yasuaki Ito and Koji Nakano
    • Journal Title

      International Journal on Foundations of Computer Science

      Volume: Vol.21, No. 3 Pages: 405-425

    • DOI

      DOI:10.1142/S0129054110007337

    • Peer Reviewed
  • [Presentation] An Algorithm to Remove Asynchronous ROMs in Circuits with Cycles2011

    • Author(s)
      Md. Nazrul Islam Mondal, Koji Nakano, and Yasuaki Ito
    • Organizer
      International Conference on Networking and Computing
    • Place of Presentation
      大阪、日本
    • Year and Date
      2011-11-30
  • [Presentation] The Parallel FDFM Processor Core Approach for Neural Networks2011

    • Author(s)
      Yuki Ago, Atsuo Inoue, Koji Nakano, and Yasuaki Ito
    • Organizer
      International Conference on Networking and Computing
    • Place of Presentation
      大阪、日本
    • Year and Date
      2011-11-30
  • [Presentation] CRT-based Decryption using DSP blocks on the Xilinx Virtex-6 FPGA2011

    • Author(s)
      Bo Song, Yasuaki Ito, and Koji Nakano
    • Organizer
      Workshop on Advances in Parallel and Distributed Computational Models
    • Place of Presentation
      アンカレッジ、米国
    • Year and Date
      2011-05-16
  • [Presentation] A Perspective on the Experiential Learning of Computer Architecture2010

    • Author(s)
      Ian McLoughlin and Koji Nakano
    • Organizer
      IEEE/ACM Int'l Conference on Cyber, Physical and Social Computing (CPSCom)
    • Place of Presentation
      杭州、中国
    • Year and Date
      2010-12-18
  • [Presentation] An RSA Encryption Hardware Algorithm Using a Single DSP Block and a Single Block RAM on the FPGA2010

    • Author(s)
      Bo Song, Kensuke Kawakami, Koji Nakano, and Yasuaki Ito
    • Organizer
      International Conference on Networking and Computing
    • Place of Presentation
      広島、日本
    • Year and Date
      2010-11-17
  • [Presentation] A Rewriting Algorithm to Generate AROM-free Fully Synchronous Circuits2010

    • Author(s)
      Md. Nazrul Islam Mondal, Koji Nakano, and Yasuaki Ito
    • Organizer
      International Conference on Networking and Computing
    • Place of Presentation
      広島、日本
    • Year and Date
      2010-11-17
  • [Presentation] Efficient Exhaustive Verification of the Collatz Conjecture using DSP48E blocks of Xilinx Virtex-5 FPGAs2010

    • Author(s)
      Yasuaki Ito, Koji Nakano
    • Place of Presentation
      アトランタ、米国
    • Year and Date
      2010-04-19
  • [Presentation] A Hardware-Software Cooperative Approach for the Exhaustive Verification of the Collatz Cojecture2009

    • Author(s)
      Yasuaki I t o , Ko ji Nakano
    • Organizer
      International Symposium on Parallel and Distributed Processing with Applications
    • Place of Presentation
      成都、中国
    • Year and Date
      2009-08-09
  • [Remarks]

    • URL

      http://www.cs.hiroshima-u.ac.jp/

URL: 

Published: 2014-08-29  

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