2011 Fiscal Year Final Research Report
A Coprocessor Architecture to Defend against Security Attacks
| Project/Area Number |
21500053
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Kyoto Institute of Technology |
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Principal Investigator |
HIRATA Hiroaki 京都工芸繊維大学, 工芸科学研究科, 准教授 (90273549)
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| Co-Investigator(Kenkyū-buntansha) |
SHIBAYAMA Kiyoshi 京都工芸繊維大学, 工芸科学研究科, 教授 (70127091)
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| Project Period (FY) |
2009 – 2011
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| Keywords | 計算機システム / システムオンチップ / インターネット高度化 / セキュア・ネットワーク |
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| Research Abstract |
We proposed a novel microprocessor architecture with a defense mechanism against stack smashing attacks, which corrupt the procedure return address and force the target computer to execute a malicious code. Our processor consists of two components ; the main processor, which executes the operating system and user applications, and the auxiliary processor, which follows the program execution in the main processor and detects the return address corruption. Consequently, our architecture achieves both detection accuracy and performance.
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