2011 Fiscal Year Final Research Report
Study on an establishment of digital circuit design using statistical timing analysis
| Project/Area Number |
21560364
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | Chuo University |
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Principal Investigator |
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| Co-Investigator(Kenkyū-buntansha) |
FUKUI Masahiro 立命館大学, 理工学部, 教授 (50367992)
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| Project Period (FY) |
2009 – 2011
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| Keywords | 回路設計・CAD / タイミング検査 / 統計的静的遅延解析 / 電源配線最適化 / クリティカルパス / ばらつき要因解析 / 遅延ばらつきライブラリ |
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| Research Abstract |
In this research, we tackled basic algorithmic problems to establish a statistical design method, and obtained the following products.
We modified our previous algorithm for statistical static timing analysis using Gaussian mixture model, so as to improve the calculated error of timing violation probability and to handle the effect of long-term degradation. Moreover, in order to make timing test efficient, we devised an algorithm to remove unnecessary paths from a given circuit, and in order to evaluate this algorithm, we devised an algorithm to calculate the criticality probability of a given path.
We devised a method to create a delay variation library which incorporates fluctuations of voltage and temperature, and a method to estimate the long-term variation. By using these methods, we devised an algorithm for finding an optimal power grid which increases overall dependability of the power grid. Moreover, we improved the simulation speed of the system for power grid analysis, which is used for our power grid synthesis.
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