2011 Fiscal Year Final Research Report
Systematic Design Scheme for Process-Variation-Free Highly Dependable Multiple-Valued VLSI
| Project/Area Number |
21700051
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
Computer system/Network
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| Research Institution | Tohoku University |
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Principal Investigator |
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| Project Period (FY) |
2009 – 2011
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| Keywords | VLSI設計技術 |
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| Research Abstract |
This research aimed to develop a systematic design scheme for process-variation-free multiple-valued VLSI. Through establishment of a high-level synthesis/verification tool for multiple-valued logic circuit, and design and performance verification of a variation-aware multiple-valued logic LSI based on nonvolatile memory device, it is confirmed to be able to realize high-performance and highly-dependable VLSIs by using the proposed method.
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