2010 Fiscal Year Final Research Report
A study on a Multi-path Memory for High-Performance Multi-core Processors
Project/Area Number |
21700055
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Research Category |
Grant-in-Aid for Young Scientists (B)
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Allocation Type | Single-year Grants |
Research Field |
Computer system/Network
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Research Institution | The University of Electro-Communications |
Principal Investigator |
KONDO Masaaki The University of Electro-Communications, 大学院・情報システム学研究科, 准教授 (30376660)
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Project Period (FY) |
2009 – 2010
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Keywords | 計算機システム / 情報システム / システムオンチップ / ハイパフォーマンス・コンピューティング / メモリシステム |
Research Abstract |
We study a multi-path main memory technique and a dynamic path-allocation mechanism to overcome the memory-wall problem for high-performance multi-core processors. Assuming high-end DRAM devices, we could not obtain enough performance improvement with our method since the performance limiter is not memory access bandwidth but latency. However, we expect a benefit of the method for future many-core processors due to its extended memory bandwidth.
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[Presentation] Geyser-1 and Geyser-2: MIPS R3000 CPU Chips with Fine-grain Runtime Power Gating2010
Author(s)
L.Zhao, D.Ikebuchi, Y.Saito, M.Kamata, N.Seki, Y.Kojima, H.Amano, S.Koyama, T.Hashida, Y.Umahashi, D.Masuda, K.Usami, T.Sunata, K.Kimura, M.Namiki, S.Takeda, H.Nakamura, M.Kondo
Organizer
IEEE Symposium on Low-Power and High-Speed Chips
Place of Presentation
横浜情報文化センター(神奈川県)
Year and Date
2010-04-16
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