A Study on Parameter Extraction Method of Carrier Transport Properties in Layered Semiconductor Substrates

2023 Fiscal Year Final Research Report

• Project/Area Number: 21K04160
• Research Category: Grant-in-Aid for Scientific Research (C)
• Allocation Type: Multi-year Fund
• Section: 一般
• Review Section: Basic Section 21050:Electric and electronic materials-related
• Research Institution: Kansai University
• Principal Investigator: Sato Shingo 関西大学, システム理工学部, 准教授 (60709137)
• Project Period (FY): 2021-04-01 – 2024-03-31
• Keywords: pseudo-MOS法 / 積層半導体基板 / Kelvin法 / 伝送線路モデル / 容量-電圧特性

Outline of Final Research Achievements

This research was initiated with the aim of developing a method for accurately evaluating the electrical properties and interface quality of semiconductor substrates with a stacked structure without the fabrication process of the semiconductor device. We clarified the essential measurement configuration and substrate conditions for extracting electrical properties using the Pseudo-MOS method, which is an evaluation method for multilayered substrates. The frequency dependence of the capacitance value was measured under these conditions, and the maximum of the capacitance value at a specific frequency observed when an AC signal propagates over the channel formed near the thin-film interface was confirmed for the first time.

Free Research Field

半導体

Academic Significance and Societal Importance of the Research Achievements

近年、活発に研究されている積層半導体基板に関して、半導体素子構造を形成することなく電気物性値を高精度に抽出する検査手法を開発することは各種材料やその積層構造開発の加速に資するものである。特に本研究を通して検査手法の高精度化に向けた測定構成・条件を明確化し、またその条件下で交流信号のチャネル上伝搬を観測できたことは界面品質に関連する検査手法の高精度化に向けた見込みを得たという点において社会的意義が大きい。