2021 Fiscal Year Research-status Report
Time-Space Re-configurable Flash Computations
| Project/Area Number |
21K11809
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| Research Institution | Nara Institute of Science and Technology |
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Principal Investigator |
ZHANG Renyuan 奈良先端科学技術大学院大学, 先端科学技術研究科, 准教授 (00709131)
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| Co-Investigator(Kenkyū-buntansha) |
木村 睦 奈良先端科学技術大学院大学, 先端科学技術研究科, 客員教授 (60368032)
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| Project Period (FY) |
2021-04-01 – 2024-03-31
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| Keywords | Continuous domain / bisection neural network / re-configurability / parameter reduction |
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| Outline of Annual Research Achievements |
In this year, both of time- and space-domains of re-censurability were investigated for computing platforms as follows: (1) stochastic computing (SC) in continuous domain. In this phase, the SC in discrete domain is migrated into continuous domain with rich benefit. In this work, the concept of continuous state machine is improved along with the circuit implementation. From the circuit simulation results, the accuracy, power, and speed of the proposed hybrid SC circuits are all similar or superior to the state-of-art. (2) Evolutions of DiaNets, addressing space-elastic. We proposed various generations of DiaNet to prevent the depth explosion and gradient vanishing problem, including I/O layer integration and skip connection (DiaNet2.0 and 3.0). Various applications are implemented.
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| Current Status of Research Progress |
Current Status of Research Progress
1: Research has progressed more than it was originally planned.
Reason
The current progress fully matches my initial proposal. All the performances of our developed platforms are superior in some specific features as (1) the stochastic computing appears the expected performances; (2) DiaNets are updated for several versions and DiaNet4.0 on-going. The research is conducted better than the expectation as: (1) from this project, we start collaborating with physicists in super conductor field and kick-off new scenario of “cool data center”by combing CMOS and AQFP on the basis of this project. The very first results will be disclosed on IEEE SOCC soon, and submitted to a patent and a journal paper. (2) A “calculator-free neural network” is under investigation and its feasibility has been verified by the works in this year.
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| Strategy for Future Research Activity |
Firstly, the quantum-spike coding methodology will be explored. The DiaNet4.0 in planning will be innovated by quantizing the data from integer to ternary. Then, the look-up table (LUT) is used for calculating instead of calculators or ALUs. Secondly, cool stochastic computing platform will be investigated as (1) the behavior of CMOS device under low temperature is investigated. (2) the simulators for adiabatic quantum-flux-parametron (AQFP) are expected to develop and improve. So far, the behavior of single AQFP device is well investigated but the stochastic implementation of AQFP has not been scientifically modeled. (3) The interface between CMOS and AQFP will be designed, which includes binary-voltage-to-analog-current converter, bias calibrator, non-linear look-up table etc.
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| Causes of Carryover |
Due to COVID-19, the supply of semi-conductor production is lack. Most of experiment equipment such as FPGA-SoC cannot be purchased during 2021. Moreover, all the business trips to international conferences were eliminated since they were held on-line. Then, the budgets are transferred to 2022 for equipment and publication charges including international conferences and journals.
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