2022 Fiscal Year Research-status Report
Time-Space Re-configurable Flash Computations
| Project/Area Number |
21K11809
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| Research Institution | Nara Institute of Science and Technology |
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Principal Investigator |
ZHANG Renyuan 奈良先端科学技術大学院大学, 先端科学技術研究科, 准教授 (00709131)
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| Co-Investigator(Kenkyū-buntansha) |
木村 睦 奈良先端科学技術大学院大学, 先端科学技術研究科, 客員教授 (60368032)
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| Project Period (FY) |
2021-04-01 – 2024-03-31
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| Keywords | Non-deterministic / bisection neural network / re-configurability / efficiency |
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| Outline of Annual Research Achievements |
In this year, both of time- and space-reconfigurable computing technologies are explored in deep as planned. 1. For time-reconfigurable computing technologies, we focus on the non-deterministic computing applications in various fields such as medicine and wireless communications. By applying the proposed stochastic computing scheme, the quality of service and robustness in some real-world scenarios are both superior to the world top performances. 2. For space reconfigurable computing technologies, the DiaNet series (the third version) have been applied in various AI tasks and archived fair or superior performances with greatly reduced cost.
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| Current Status of Research Progress |
Current Status of Research Progress
1: Research has progressed more than it was originally planned.
Reason
The current progress fully matches my initial proposal. All of three tiers including mechanism, circuits, and application levels have been explored, and the performances of our developed platforms are superior in some specific features. Moreover, a new technology for data-coding was developed beyond the initial plan, which accelerates the computations greatly. The relevant research progresses were published on world top-class transactions and conference such as IEEE TNNLS and IJCAI. The proposed technologies appear potentials on solving the real-world problems such as medicine and wireless communications. The next step of this project is well indicated on the basis of progress of this year. From the current results, the “calculator free NN inference” becomes feasible as initially planned.
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| Strategy for Future Research Activity |
Firstly, the quantum-spike coding methodology will be explored. We are going to start from some toy-examples such as conventional neural networks. Two schemes including one-shot observation and statistic observation are verified to perform regression and pattern recognition. Then, we will migrate this coding methodology into our DiaNet. Secondly and simultaneously, more series of DiaNet (so far, till version 3.1) and flash computing architecture are expected to evolve. As soon as above techniques ready, we might migrate some existing tensor computing structures such as systolic ring by partitioning the DiaNet into reasonable pieces. As the further step rooting on this project, it is expected to develop the CMOS-superconductor hybrid computing platforms.
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| Causes of Carryover |
Due to the COVID-19, most of international conferences are held on-line. The budget planned for business trips was not occupied. Moreover, the purchase plan of FPGA board and GPU is delayed due to the lack of semi-conductor devices globally. Then, the FPGA SoC and GPU are planned to be purchased in the next fiscal year (2023). For presenting the research results from this project, several papers are planned to be presented on international conferences from this budget.
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