2021 Fiscal Year Research-status Report
A Novel Power Reduction Technique Using Error-resilient Deep Neural Networks for STT-MRAM Based Energy-efficient Brain-inspired Processor Design
| Project/Area Number |
21K17719
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| Research Institution | Tohoku University |
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Principal Investigator |
李 涛 東北大学, 工学研究科, 助教 (20794952)
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| Project Period (FY) |
2021-04-01 – 2023-03-31
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| Keywords | Neural Networks / Error Resilient / STT-MRAM / Brain-inspired Processor / Energy-efficient |
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| Outline of Annual Research Achievements |
In exploring the error resilience of the neural network in reducing the power consumption of STT-MRAM, the applicant discovered that the circuit architecture of the processing module in the circuit has an essential impact on the power consumption of brain-inspired processors and the error characteristics of neural network. The applicant proposes that the whole neural network adopts the same fixed-point representation format, and it has no impact on the accuracy of the neural network. The applicant proposed the convolution module based on a hybrid bit multiplier, the convolution module based on a divide-and-conquer multiplier, and the adaptive quantization module embedded in the multiplier. The applicant promoted the project from two aspects: algorithm and circuit design.
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| Current Status of Research Progress |
Current Status of Research Progress
3: Progress in research has been slightly delayed.
Reason
In the next step, the applicant will continue to promote the project according to the plan proposed in the application material. Firstly, the error map of STT-MRAM will be used to evaluate its impact on different neural networks and explore an optimal fault tolerance. Then, the influence of the switching current corresponding to the optimal fault tolerance on the power consumption of STT-MRAM is evaluated. Promote the implementation of the project from two aspects: algorithm and chip simulation.
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| Strategy for Future Research Activity |
The applicant found that the error resiliency of neural networks is related to the algorithm and the circuit architecture in brain-inspired processor design. While exploring the error resiliency characteristics of the neural network, the applicant also spent some time on the circuit architecture design. Therefore, there is a slight delay in evaluating the error resilience of the neural network, but there is a breakthrough in circuit architecture, which exceeds the applicant's expectation.
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| Causes of Carryover |
This fiscal year's research mainly utilizes the mobile Workstation for algorithm simulation and circuit design. Due to the current shortage of semiconductors, the HP Zbook 17 previously planned to be purchased was out of stock, so its substitute, Dell 7760, was purchased. The major work in the next fiscal year will be to transplant algorithms to the FPGA development board for testing, so it is planned to buy an FPGA development board, oscilloscope and other test instruments.
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Research Products
(2 results)
