2022 Fiscal Year Research-status Report
A Novel Power Reduction Technique Using Error-resilient Deep Neural Networks for STT-MRAM Based Energy-efficient Brain-inspired Processor Design
| Project/Area Number |
21K17719
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| Research Institution | Tohoku University |
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Principal Investigator |
李 涛 東北大学, 工学研究科, 助教 (20794952)
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| Project Period (FY) |
2021-04-01 – 2024-03-31
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| Keywords | Neural Networks / Error-resilient / STT-MRAM / Brain-inspired Processor / Energy-efficient |
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| Outline of Annual Research Achievements |
This year, we continued our study on the adaptive quantization algorithm and validated its influence on AI chip performance in terms of algorithms and circuit architecture. A novel adaptive and low-power quantization technique and systematically validates its effectiveness from the algorithm to the hardware module for industrial IoT applications, covering precise navigation for autonomous vehicles and accurate classification utilizing deep neural networks. The proposed quantization method merges an adaptive conversion function from floating-point to fixed-point binaries with an adaptive radix-point determination function, ensuring adequate resolution and minimal error loss of the fixed-point inputs to the edge AI modules. In addition, a hybrid signed convolution module with the architecture of an unsigned divide-and-conquer multiplier is proposed to improve the functional diversity and energy efficiency of artificial intelligence accelerators based on STT-MRAM. The proposed multiplier framework enables different multiplication modes, considerably enhancing the multiplier's versatility for next-generation AI accelerators.
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| Current Status of Research Progress |
Current Status of Research Progress
3: Progress in research has been slightly delayed.
Reason
The applicant has achieved substantial advancements in the design of hardware circuits for brain-inspired processors using the error-resilient neural network algorithm. Nevertheless, the impact of COVID-19 on the semiconductor deficit has caused delays in the purchase of some hardware devices, therefore delaying the hardware system's development.
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| Strategy for Future Research Activity |
This year, the applicant achieved major achievements in designing quantization and convolutional circuits for brain-inspired processors. Throughout the next year, the applicant will keep developing the subsequent design of the brain-inspired processor circuit, such as the activation function approximation and hardwareization.
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| Causes of Carryover |
I focused on quantization algorithms, hardware design, and system demonstration preparation this year; therefore, I purchased books on circuit design, software licenses for circuit design, laptops, and cameras. In the next year, I will continue circuit design, system development, and publishing of research results, as well as buy equipment for system demonstration and testing and pay publication and conference travel costs.
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