In-Storage Accelerator Architectures for Large-Scale Sparse Matrix Processing

2023 Fiscal Year Final Research Report

• Project/Area Number: 21K17720
• Research Category: Grant-in-Aid for Early-Career Scientists
• Allocation Type: Multi-year Fund
• Review Section: Basic Section 60040:Computer system-related
• Research Institution: Tokyo Institute of Technology
• Principal Investigator: Chu Thiem Van 東京工業大学, 科学技術創成研究院, 助教 (80838235)
• Project Period (FY): 2021-04-01 – 2024-03-31
• Keywords: 疎行列処理 / 疎行列疎行列積 / データフロー / アーキテクチャ / FPGA

Outline of Final Research Achievements

This study aims to develop a comprehensive sparse matrix processing architecture, including an in-storage accelerator architecture, to perform large-scale sparse matrix processing with high performance and efficiency. As the first step, the research focuses on the basic operation of sparse-sparse matrix multiplication, advancing the study of a high-performance and efficient architecture, and implementing and evaluating a hardware prototype using FPGA (Field-Programmable Gate Array). Major achievements include the presentation of a paper at the Asia and South Pacific Design Automation Conference (ASP-DAC'24), three invited talks, and two awards.

Free Research Field

計算機システム

Academic Significance and Societal Importance of the Research Achievements

本研究の成果は，疎行列処理の高速化と高効率化を実現することで，ビッグデータ解析，機械学習，科学計算の複雑なシミュレーションなど多くのアプリケーションにおいて重要な計算カーネルの性能向上および計算資源の節約に寄与する．本研究によって提案された手法は，学術的にはアーキテクチャおよびハードウェア設計に新たな知見を提供し，社会的にはデータ分析や人工知能などの発展に大きな影響を与えると期待できる．