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2013 Fiscal Year Annual Research Report

断熱モード単一磁束量子回路の導入によるサブμWマイクロプロセッサの研究

Research Project

Project/Area Number 22226009
Research InstitutionYokohama National University

Principal Investigator

吉川 信行  横浜国立大学, 工学研究院, 教授 (70202398)

Co-Investigator(Kenkyū-buntansha) 藤巻 朗  名古屋大学, 工学(系)研究科(研究院), 教授 (20183931)
日高 睦夫  独立行政法人産業技術総合研究所, ナノエレクトロニクス研究部門, 上級主任研究員 (20500672)
Project Period (FY) 2010-05-31 – 2015-03-31
Keywords超伝導材料・素子 / 先端機能デバイス / 低消費電力 / 超高速情報処理 / デバイス設計・製造プロセス / 超伝導回路 / ジョセフソン素子 / 集積回路
Research Abstract

これまでに得られたSFQ回路の低消費電力化のための各種基本要素技術を結集し、セルライブラリを完成させた。更にセルライブラリを用いて各種演算回路を試作し、低消費電力型SFQ回路用セルライブラリの有効性を評価した。
横浜国大では昨年度までに得られた断熱モードSFQ回路の動作余裕度、入力感度、回路バラツキに対する耐性に基づいて、基本ゲートの回路パラメータを決定した。またこのパラメータに基づいてNOTゲート、Majorityゲートを試作し、その正常動作を確認した。以上に基づき断熱モードSFQ回路のセルライブラリを構築した。また、セルライブラリを用いて1b全加算器を設計試作し、十分に広い動作マージンでの回路の正常動作を実証した。加えて断熱型SFQ回路を用いたフリップフロップを提案し、回路の動作実証を行なった。
名古屋大ではインダクティブロード技術を導入し、駆動電圧を従来の1/5である0.5 mVまで低減化した単一磁束量子回路を用いてビットシリアルアーキテクチャの8ビットマイクロプロセッサを設計した。また、受動線路技術を駆使して、必要なジョセフソン接合を削減した。産総研のADP2プロセスを利用し、試作・測定した結果、消費電力は従来の1/7の170μW、動作周波数は2倍の30GHzに向上した。また、CMOSアンプを60Kステージに設置できるよう冷凍機の改造を進めた。現在特性評価中である。
産総研では、面積従来比1/5のジョセフソン接合を集積回路プロセスに適用するにために均一性、再現性の面から最も適した作製方法の検討を行った。CMP平坦化を用いる方法は、面積従来比1/10以下の極微細接合を作製可能であるが、所望の均一性、再現性を得るためにはより高度な装置が必要であることがわかった。一方、コンタクトホール結合型円形接合は、面積従来比1/5レベルの接合作製において集積回路に適用可能なレベルの均一性、再現性が得られることを明らかにした。

Current Status of Research Progress
Current Status of Research Progress

1: Research has progressed more than it was originally planned.

Reason

これまでに、断熱モードSFQ回路においては、セルライブラリを構築し、1ビット全加算器の動作実証に成功した他、断熱型SFQ回路を用いたフリップフロップの提案と回路の動作実証を行なった。以上により、サブμWマイクロプロセッサの実現に向けた基盤技術がほぼ確立できた。
インダクティブロード技術を用いた低電圧駆動SFQ回路においては、従来の1/7の消費電力で動作する8ビットマイクロプロセッサの30GHz動作実証に成功した。
微細化接合プロセスの研究においては、従来の1/5のレベルの微細接合が、均一かつ再現性よく得られることを明らかにできた。
以上の成果は、当初の研究計画を十分以上に達成している。

Strategy for Future Research Activity

本年度は、これまでに開発した低消費電力型SFQ回路のセルライブラリを用いてマイクロプロセッサを設計試作し、低消費電力SFQマイクロプロセッサの動作実証を目指す。これにより、SFQ集積回路技術の有効性を示す。インダクティブロードを導入した準断熱動作SFQ回路においては、50μW, 30GHz動作マイクロプロセッサの動作実証を行う。また、断熱動作SFQ回路においては、8b carry look-ahead加算器などの演算回路の動作実証を通してサブμWマイクロプロセッサを実現するための基盤技術を確立する。

  • Research Products

    (75 results)

All 2014 2013 Other

All Journal Article (13 results) (of which Peer Reviewed: 13 results) Presentation (61 results) (of which Invited: 9 results) Remarks (1 results)

  • [Journal Article] 消費電力の限界に挑む超電導集積回路技術の最近の進展2014

    • Author(s)
      吉川信行
    • Journal Title

      電学論A

      Volume: 134 Pages: 14-17

    • Peer Reviewed
  • [Journal Article] Design and Evaluation of Magnetic Field Tolerant Single Flux Quantum Circuits for Superconductive Sensing Systems2014

    • Author(s)
      Y. Yamanashi, N. Yoshikawa
    • Journal Title

      IEICE Trans. Electron.

      Volume: E97-C Pages: 178-181

    • DOI

      10.1587/transele.E97.C.178

    • Peer Reviewed
  • [Journal Article] Design and Demonstration of a Single-Flux-Quantum Multi-Stop Time-to-Digital Converter for Time-of-Flight Mass Spectrometry2014

    • Author(s)
      K. Sano, Y. Yamanashi, N. Yoshikawa
    • Journal Title

      IEICE Trans. Electron.

      Volume: E97-C Pages: 182-187

    • DOI

      10.1587/transele.E97.C.182

    • Peer Reviewed
  • [Journal Article] A Reconfigurable Data-Path Accelerator Based on Single Flux Quantum Circuits2014

    • Author(s)
      H. Kataoka, H. Honda, F. Mehdipour, N. Yoshikawa, A. Fujimaki, H. Akaike, N. Takagi, K. Murakami
    • Journal Title

      IEICE Trans. Electron.

      Volume: E97-C Pages: 141-148

    • DOI

      10.1587/transele.E97.C.141

    • Peer Reviewed
  • [Journal Article] Nb 9-layer fabrication process for superconducting large-scale SFQ circuits and its process evaluation2014

    • Author(s)
      S. Nagasawa, K. Hinode, T. Satoh, M. Hidaka, H. Akaike, A. Fujimaki, N. Yoshikawa, K. Takagi, N. Takagi
    • Journal Title

      IEICE Trans. Electron.

      Volume: E97-C Pages: 132-140

    • DOI

      10.1587/transele.E97.C.132

    • Peer Reviewed
  • [Journal Article] Design and High-Speed Demonstration of Single-Flux-Quantum Bit-Serial Floating-Point Multipliers Using a 10kA/cm2 Nb Process2014

    • Author(s)
      X. Peng, Y. Yamanashi, N. Yoshikawa, A. Fujimaki, N. Takagi, K. Takagi, M. Hidaka
    • Journal Title

      IEICE Trans. Electron.

      Volume: E97-C Pages: 188-193

    • DOI

      10.1587/transele.E97.C.188

    • Peer Reviewed
  • [Journal Article] Large-Scale Integrated Circuit Design Based on a Nb Nine-Layer Structure for Reconfigurable Data-Path Processors2014

    • Author(s)
      A. Fujimaki, M. Tanaka, R. Kasagi, K. Takagi, M. Okada, Y. Hayakawa, K. Takata, H. Akaike, N. Yoshikawa, S. Nagasawa, K. Takagi, N. Takagi
    • Journal Title

      IEICE Trans. Electron.

      Volume: E97-C Pages: 157-165

    • DOI

      10.1587/transele.E97.C.157

    • Peer Reviewed
  • [Journal Article] High-Speed Operation of 0.25-mV RSFQ Arithmetic Logic Unit Based on 10-kA/cm2 Nb Process Technology2014

    • Author(s)
      M. Tanaka, A. Kitayama, M. Okada, T. Kouketsu, T. Takinami, M. Ito, A. Fujimaki
    • Journal Title

      IEICE Trans. Electron.

      Volume: E97-C Pages: 166-172

    • DOI

      10.1587/transele.E97.C.166

    • Peer Reviewed
  • [Journal Article] Novel latch for adiabatic quantum-flux-parametron logic2014

    • Author(s)
      N. Takeuchi, T. Ortlepp, Y. Yamanashi, N. Yoshikawa
    • Journal Title

      Journal of Applied Physics

      Volume: 115 Pages: 103910

    • DOI

      10.1063/1.4868336

    • Peer Reviewed
  • [Journal Article] Operation of an Adiabatic Quantum-Flux-Parametron Gate Using an On-chip AC Power Source2013

    • Author(s)
      T. Mukaiyama, N. Takeuchi, Y. Yamanashi and N. Yoshikawa
    • Journal Title

      IEEE Trans. Appl. Supercond.

      Volume: 23 Pages: 1301605

    • DOI

      10.1109/TASC.2013.2251465

    • Peer Reviewed
  • [Journal Article] Low-Energy Consumption RSFQ Circuits Driven by Low Voltages2013

    • Author(s)
      M. Tanaka, A. Kitayama, T.Kouketsu, M. Ito, and A. Fujimaki
    • Journal Title

      IEEE Trans. on Appl. Supercond.

      Volume: 23 Pages: 1701104

    • DOI

      10.1109/TASC.2013.2240555

    • Peer Reviewed
  • [Journal Article] Device Yield in Nb-Nine-Layer Circuit Fabrication Process2013

    • Author(s)
      M. Hidaka, S. Nagasawa, K. Hinode, T. Satoh
    • Journal Title

      IEEE Trans. Appl. Supercond.

      Volume: 23 Pages: 1100906

    • DOI

      10.1109/TASC.2012.1137471

    • Peer Reviewed
  • [Journal Article] Simulation of sub-kBT bit-energy operation of adiabatic quantum-flux parametron logic with low bit-error-rate2013

    • Author(s)
      N. Takeuchi, Y. Yamanashi and N. Yoshikawa
    • Journal Title

      Appl. Phys. Lett.

      Volume: 103 Pages: 062602

    • DOI

      10.1063/1.4817974

    • Peer Reviewed
  • [Presentation] Adiabatic Superconducting Circuits and Reversible Computing2014

    • Author(s)
      N. Yoshikawa
    • Organizer
      Superconducting SFQ VLSI Workshop for Young Scientists (SSV 2014-YS)
    • Place of Presentation
      Nagoya, Japan
    • Year and Date
      20140305-20140307
    • Invited
  • [Presentation] Energy-Efficient Superconductor Circuits and Applications2014

    • Author(s)
      A. Fuimaki
    • Organizer
      Superconducting SFQ VLSI Workshop for Young Scientists (SSV 2014-YS)
    • Place of Presentation
      Nagoya, Japan
    • Year and Date
      20140305-20140307
  • [Presentation] Fabrication process and Device Structures for Nb-based Integrated circuits2014

    • Author(s)
      M. Hidaka
    • Organizer
      Superconducting SFQ VLSI Workshop for Young Scientists (SSV 2014-YS)
    • Place of Presentation
      Nagoya, Japan
    • Year and Date
      20140305-20140307
    • Invited
  • [Presentation] 磁気シールド構造を用いた断熱型磁束量子パラメトロンによる8-bit Carry Look-ahead Adderの設計と測定結果2013

    • Author(s)
      井上健太、竹内尚輝、山梨裕希、吉川 信行
    • Organizer
      2013 年度秋季低温工学・超電導学会
    • Place of Presentation
      ウインクあいち(名古屋市)
    • Year and Date
      20131204-20131206
  • [Presentation] Circuit Design of Zero-Static Power SFQ Circuit Using Magnetic Flux Biasing2013

    • Author(s)
      Y. Yamanashi, R. Tsutsumi, N. Yoshikawa
    • Organizer
      Superconducting SFQ VLSI Workshop (SSV2013)
    • Place of Presentation
      Tsukuba, Japan
    • Year and Date
      20131121-20131122
  • [Presentation] Several Applications Using Quantum-Flux-Latches2013

    • Author(s)
      N. Takeuchi, T. Ortlepp, Y. Yamanashi, N. Yoshikawa
    • Organizer
      Superconducting SFQ VLSI Workshop (SSV2013)
    • Place of Presentation
      Tsukuba, Japan
    • Year and Date
      20131121-20131122
  • [Presentation] Design and Implementation of a High Sensitive DC/SFQ Converter2013

    • Author(s)
      K. Sato, Y. Yamanashi, N. Yoshikawa
    • Organizer
      Superconducting SFQ VLSI Workshop (SSV2013)
    • Place of Presentation
      Tsukuba, Japan
    • Year and Date
      20131121-20131122
  • [Presentation] Improvement of Interface Circuit for Josephson/CMOS Hybrid Memories toward Ground-Current Reduction and Low Power Dissipation2013

    • Author(s)
      X. Peng, Y.Sasaki, Y. Yamanashi, N. Yoshikawa
    • Organizer
      Superconducting SFQ VLSI Workshop (SSV2013)
    • Place of Presentation
      Tsukuba, Japan
    • Year and Date
      20131121-20131122
  • [Presentation] New Design Method of Single Flux Quantum Logic Circuits Using Dynamically Reconfigurable Logic Gates2013

    • Author(s)
      S. Nishimoto, Y. Yamanashi, N. Yoshikawa
    • Organizer
      Superconducting SFQ VLSI Workshop (SSV2013)
    • Place of Presentation
      Tsukuba, Japan
    • Year and Date
      20131121-20131122
  • [Presentation] Improvement of Performance of a Superconductive Random Number Generator by Optimization of Parameters2013

    • Author(s)
      S. Hachiya, Y. Yamanashi, N. Yoshikawa
    • Organizer
      Superconducting SFQ VLSI Workshop (SSV2013)
    • Place of Presentation
      Tsukuba, Japan
    • Year and Date
      20131121-20131122
  • [Presentation] Improvement of Slew Rate High-Sensitive Superconductive Digital Magnetomerter2013

    • Author(s)
      F. China, Y. Yamanashi, N. Yoshikawa
    • Organizer
      Superconducting SFQ VLSI Workshop (SSV2013)
    • Place of Presentation
      Tsukuba, Japan
    • Year and Date
      20131121-20131122
  • [Presentation] Imprementation of an Integer-based Hardware-Algorithm in Single-Flux-Quantum Electronics2013

    • Author(s)
      Q. Xu, Y. Yamanashi, N. Yoshikawa, T. Ortlepp
    • Organizer
      Superconducting SFQ VLSI Workshop (SSV2013)
    • Place of Presentation
      Tsukuba, Japan
    • Year and Date
      20131121-20131122
  • [Presentation] Design and Test of Basic Cells for Adiabatic Quantum-Flux-Parametron Logic with Magnetic-Shielding Structures2013

    • Author(s)
      K. Inoue, N. Takeuchi,Y. Yamanashi, N. Yoshikawa
    • Organizer
      Superconducting SFQ VLSI Workshop (SSV2013)
    • Place of Presentation
      Tsukuba, Japan
    • Year and Date
      20131121-20131122
  • [Presentation] Design of an SFQ Butterfly Ciecuit for Signed Number Operation Using the Nb 10 kA/cm2 Josephson Process2013

    • Author(s)
      Y. Sakashita, Y. Yamanashi, N. Yoshikawa
    • Organizer
      Superconducting SFQ VLSI Workshop (SSV2013)
    • Place of Presentation
      Tsukuba, Japan
    • Year and Date
      20131121-20131122
  • [Presentation] Improvement of Decoders and Data Divers in Terms of Power Consumption for 64-kb SFQ/CMOS Hybrid Memories2013

    • Author(s)
      Y. Sasaki, X. Pen, T. Nishimura, Y. Yamanashi, N. Yoshikawa
    • Organizer
      Superconducting SFQ VLSI Workshop (SSV2013)
    • Place of Presentation
      Tsukuba, Japan
    • Year and Date
      20131121-20131122
  • [Presentation] Development of Single-Flux-Quantum Multi-Threshold Current Discriminators for m/z-Sensitive Time-of-Flight Mass Spectrometry2013

    • Author(s)
      Y. Muramatsu, K. Sano, Y. Yamanashi, N. Yoshikawa
    • Organizer
      Superconducting SFQ VLSI Workshop (SSV2013)
    • Place of Presentation
      Tsukuba, Japan
    • Year and Date
      20131121-20131122
  • [Presentation] Evaluation of Serially Biased SFQ Circuits Using Floating Ground Plane Structures2013

    • Author(s)
      A. Takahashi, Y. Yamanashi, N. Yoshikawa
    • Organizer
      Superconducting SFQ VLSI Workshop (SSV2013)
    • Place of Presentation
      Tsukuba, Japan
    • Year and Date
      20131121-20131122
  • [Presentation] Development of Low-Power Shift-Register Memories Using Josephson-Junction-Biasing SFQ Circuits2013

    • Author(s)
      R. Numaguchi, A. Takahashi, Y. Yamanashi, N. Yoshikawa
    • Organizer
      Superconducting SFQ VLSI Workshop (SSV2013)
    • Place of Presentation
      Tsukuba, Japan
    • Year and Date
      20131121-20131122
  • [Presentation] Measurement of Driver and Receiver Circuits of Passive Transmission Lines in Low-Voltage Rapid-Single-Flux-Quantum Circuits2013

    • Author(s)
      T. Takinami, M. Ito, Y. Komura, M. Tanaka, A. Fujimaki
    • Organizer
      Superconducting SFQ VLSI Workshop (SSV2013)
    • Place of Presentation
      Tsukuba, Japan
    • Year and Date
      20131121-20131122
  • [Presentation] Investigation of Small Size Trilayer Josephson Junctions2013

    • Author(s)
      M. Hidaka, S. Nagasawa, T. Satoh, M. Maezawa, Y. Noguchi, M. Yamagishi, T. Horikawa
    • Organizer
      Superconducting SFQ VLSI Workshop (SSV2013)
    • Place of Presentation
      Tsukuba, Japan
    • Year and Date
      20131121-20131122
  • [Presentation] Recent Developments on Ultra-Low-Energy Adiabatic Quantum-Flux-Parametron Logic2013

    • Author(s)
      N. Yoshikawa, N. Takeuchi, K. Inoue and Y. Yamanashi
    • Organizer
      26th International Symposium on Superconductivity (ISS 2013)
    • Place of Presentation
      Tokyo, Japan
    • Year and Date
      20131118-20131120
    • Invited
  • [Presentation] Study on the Reduction of the Jitter of an Signe-Flux-Quantum Time-To-Digital Converter for Time-of-Flight Mass Spectrometry2013

    • Author(s)
      K. Sano, Y. Yamanashi, N. Yoshikawa
    • Organizer
      26th International Symposium on Superconductivity (ISS 2013)
    • Place of Presentation
      Tokyo, Japan
    • Year and Date
      20131118-20131120
  • [Presentation] Proposal and Implementation of High-Speed Test Circuits for Adiabatic Quantum-Flux-Parametron Gates2013

    • Author(s)
      N. Takeuchi, T. Ortlepp, K. Inoue, Y. Yamanashi, N. Yoshikawa
    • Organizer
      26th International Symposium on Superconductivity (ISS 2013)
    • Place of Presentation
      Tokyo, Japan
    • Year and Date
      20131118-20131120
  • [Presentation] Yield Analysis of Large-Scase Adiabatic-Quantum-Flux-Parametron Logic:The Effect of the Distribution of the Critical Current2013

    • Author(s)
      D. Si, N. Takeuchi, K.Inoue, Y. Yamanashi, N. Yoshikawa
    • Organizer
      26th International Symposium on Superconductivity (ISS 2013)
    • Place of Presentation
      Tokyo, Japan
    • Year and Date
      20131118-20131120
  • [Presentation] Design and implementation of low-power, high-density RSFQ shift-registers for random access memories2013

    • Author(s)
      M. Tanaka, A. Fujimaki
    • Organizer
      26th International Symposium on Superconductivity (ISS 2013)
    • Place of Presentation
      Tokyo, Japan
    • Year and Date
      20131118-20131120
  • [Presentation] Sub-KBT Bit-Energy Operation of Superconducting Logic: What is the Minimum Energy Bound in the Computation?2013

    • Author(s)
      N. Yoshikawa
    • Organizer
      East Asia Symposium on Superconductor Electronics (EASSE2013)
    • Place of Presentation
      Taiwan Normal University, Taipei
    • Year and Date
      20131023-20131026
  • [Presentation] Sub-kBT Bit-Energy Operation of Superconducting Logic Devices using Adiabatic Quantum Flux ParametronExtended2013

    • Author(s)
      N. Yoshikawa, N. Takeuchi, K. Inoue and Y. Yamanashi
    • Organizer
      Abstracts of the 2013 International Conference on Solid State Devices and Materials (SSDM 2013)
    • Place of Presentation
      Fukuoka, Japan
    • Year and Date
      20130924-20130927
  • [Presentation] Sub-Milliwatt, 30-GHz Microprocessor Based on Low-Voltage Rapid Single-Flux-Quantum Circuit Technology2013

    • Author(s)
      M. Tanaka, Y. Hayakawa, K. Takata and A. Fujimaki
    • Organizer
      Abstracts of the 2013 International Conference on Solid State Devices and Materials (SSDM 2013)
    • Place of Presentation
      Fukuoka, Japan
    • Year and Date
      20130924-20130927
  • [Presentation] Design and High-Speed Demonstration of SFQ Bit-Serial Floating-Point Multipliers Using ISTEC 10 kA/cm2 Nb Process

    • Author(s)
      X. Peng, Y. Shimamura, Y. Yamanashi, N. Yoshikawa, A. Fujimaki, K. Takagi, N. Takagi, S. Nagasawa
    • Organizer
      International Superconductive Electronics Conference (ISEC2013)
    • Place of Presentation
      Cambridge, USA
    • Invited
  • [Presentation] Novel Latch for Adiabatic Quantum-Flux-Parametron Logic

    • Author(s)
      N. Takeuchi, T. Ortlepp, Y. Yamanashi, N. Yoshikawa
    • Organizer
      International Superconductive Electronics Conference (ISEC2013)
    • Place of Presentation
      Cambridge, USA
  • [Presentation] Modelling and calibration of ADP process for inductance calculation with InductEx

    • Author(s)
      Coenrad J. Fourie, X. Peng, A. Takahashi, N. Yoshikawa
    • Organizer
      International Superconductive Electronics Conference (ISEC2013)
    • Place of Presentation
      Cambridge, USA
  • [Presentation] Simulation and implementation of an 8-bit carry look-ahead adder using adiabatic quantum-flux-parametron logic

    • Author(s)
      K. Inoue, N. Takeuchi, K. Ehara, Y. Yamanashi, N. Yoshikawa
    • Organizer
      International Superconductive Electronics Conference (ISEC2013)
    • Place of Presentation
      Cambridge, USA
  • [Presentation] 60-GHz Demonstration of an SFQ Half-Precision Bit-Serial Floating-Point Adder Using 10 kA/cm2 Nb Process

    • Author(s)
      T. Kato, Y. Yamanashi, N. Yoshikawa, A. Fujimaki, N. Takagi, K. Takagi, S. Nagasawa
    • Organizer
      International Superconductive Electronics Conference (ISEC2013)
    • Place of Presentation
      Cambridge, USA
  • [Presentation] Energy Dissipation and Bit-Error-Rate of Adiabatic Quantum-Flux-Parametron Logic with Under-Damped Junctions

    • Author(s)
      N. Takeuchi, Y. Yamanashi, N. Yoshikawa
    • Organizer
      International Superconductive Electronics Conference (ISEC2013)
    • Place of Presentation
      Cambridge, USA
  • [Presentation] High-speed demonstration of an integer-based hardware-algorithm using energy-efficient single-flux-quantum circuits

    • Author(s)
      Q. Xu, Y. Shimamura, N. Yoshikawa, T. Ortlepp
    • Organizer
      International Superconductive Electronics Conference (ISEC2013)
    • Place of Presentation
      Cambridge, USA
  • [Presentation] High-speed measurement of serially biased large-scale SFQ circuits

    • Author(s)
      Takahashi, Y. Yamanashi, N. Yoshikawa
    • Organizer
      International Superconductive Electronics Conference (ISEC2013)
    • Place of Presentation
      Cambridge, USA
  • [Presentation] New superconductive digital magnetometer with sub-flux quantum resolution

    • Author(s)
      F. China, Y. Yamanashi, N. Yoshikawa
    • Organizer
      International Superconductive Electronics Conference (ISEC2013)
    • Place of Presentation
      Cambridge, USA
  • [Presentation] Novel multiple input single flux quantum merge circuit using serially connected dc-SQUIDs

    • Author(s)
      K. Sato, Y. Yamanashi, N. Yoshikawa
    • Organizer
      International Superconductive Electronics Conference (ISEC2013)
    • Place of Presentation
      Cambridge, USA
  • [Presentation] Magnetic field tolerant single-flux-quantum circuit for superconducting sensing system

    • Author(s)
      Y. Yamanashi, Y. Tsuga, N. Yoshikawa
    • Organizer
      International Superconductive Electronics Conference (ISEC2013)
    • Place of Presentation
      Cambridge, USA
  • [Presentation] Design and High-Speed Tests of a Single-Flux-Quantum Time-to-Digital Converter for Time-of-Flight Mass Spectrometry

    • Author(s)
      K. Sano, A. Takahashi, Y. Yamanashi, N. Yoshikawa, N. Zen, K. Suzuki, M. Ohkubo
    • Organizer
      International Superconductive Electronics Conference (ISEC2013)
    • Place of Presentation
      Cambridge, USA
  • [Presentation] Demonstration of Fully Functional 64-kb Josephson/CMOS Hybrid Memory

    • Author(s)
      X. Peng, Y. Sasaki, H. Jin, K. Kuwabara, Y. Yamanashi, N. Yoshikawa
    • Organizer
      International Superconductive Electronics Conference (ISEC2013)
    • Place of Presentation
      Cambridge, USA
  • [Presentation] Bit error rate in low-voltage RSFQ circuits with small critical currents/lowered bias voltages

    • Author(s)
      M. Tanaka, A. Kitayama, T. Takinami, Y. Komura, A. Fujimaki,
    • Organizer
      International Superconductive Electronics Conference (ISEC2013)
    • Place of Presentation
      Cambridge, USA
  • [Presentation] Research trend of superconductor digital electronics in Japan

    • Author(s)
      A. Fujimaki, N. Yoshikawa, M. Hidaka
    • Organizer
      International Superconductive Electronics Conference (ISEC2013)
    • Place of Presentation
      Cambridge, USA
    • Invited
  • [Presentation] A Method to Provide Bias Current for Large-Scale SFQ Circuitsusing Locally Isolated Ground Planes

    • Author(s)
      X. Peng, H.Suzuki, Y.Yamanashi, N. Yoshikawa
    • Organizer
      European Conference on Applied Superconductivity (Eucas2013)
    • Place of Presentation
      Genova, Italy
  • [Presentation] Purely reversible quantum-flux-parametron logic

    • Author(s)
      N. Takeuchi, Y. Ymanashi, N. Yoshikawa
    • Organizer
      European Conference on Applied Superconductivity (Eucas2013)
    • Place of Presentation
      Genova, Italy
  • [Presentation] Design of Low-Voltage RSFQ Microprocessor Prototypes

    • Author(s)
      M. Tanaka, Y. Hayakawa, K. Takata, A. Fujimaki
    • Organizer
      European Conference on Applied Superconductivity (Eucas2013)
    • Place of Presentation
      Genova, Italy
  • [Presentation] アンダーダンプ接合を用いた断熱型QFP回路の消費エネルギーとビットエラーレートの評価

    • Author(s)
      竹内尚輝、山梨裕希、吉川信行
    • Organizer
      日本学術振興会超伝導エレクトロニクス第146委員会通信・情報処理分科会第9回研究会
    • Place of Presentation
      機械振興会館
  • [Presentation] 極限的低エネルギー動作を実現する断熱型超伝導回路とその可逆演算動作の可能性

    • Author(s)
      吉川信行
    • Organizer
      日本学術振興会超伝導エレクトロニクス第146委員会通信・情報処理分科会第9回研究会
    • Place of Presentation
      機械振興会館
    • Invited
  • [Presentation] 断熱型量子磁束パラメトロンのパラメータばらつき及び配線インダクタンスが回路動作に及ぼす影響の研究

    • Author(s)
      司徳永、竹内尚輝、井上健太、山梨裕希、吉川信行
    • Organizer
      第74回応用物理学会秋季学術講演会
    • Place of Presentation
      同志社大学京田辺キャンパス(京都府)
  • [Presentation] アンダーダンプ接合を用いた断熱型QFP回路の有限温度におけるビットエネルギー

    • Author(s)
      竹内尚輝、井上健太、山梨裕希、吉川信行
    • Organizer
      第74回応用物理学会秋季学術講演会
    • Place of Presentation
      同志社大学京田辺キャンパス(京都府)
  • [Presentation] 断熱型QFP回路の安定動作に向けたシールド構造の研究

    • Author(s)
      井上健太、竹内尚輝、山梨裕希、吉川信行
    • Organizer
      電子情報通信学会2013年ソサイエティ大会
    • Place of Presentation
      福岡工業大学(福岡市)
  • [Presentation] 64-kb SFQ/CMOSハイブリッドメモリの測定と評価

    • Author(s)
      佐々木悠太、彭 析竹、西村考正、山梨裕希、吉川信行
    • Organizer
      電子情報通信学会2013年ソサイエティ大会
    • Place of Presentation
      福岡工業大学(福岡市)
  • [Presentation] 10 kA/cm2 Nbプロセスにおけるキャパシタンスを付加したJosephson接合のEscape Rate測定

    • Author(s)
      室 健太郎、向山隆志、山梨裕希、吉川信行
    • Organizer
      電子情報通信学会2013年ソサイエティ大会
    • Place of Presentation
      福岡工業大学(福岡市)
  • [Presentation] 超伝導ストリップ線イオン検出器を用いた飛行時間分析装置のための単一磁束量子読みだし回路の研究

    • Author(s)
      吉川信行、佐野京佑、山梨裕希、全伸幸、大久保雅隆
    • Organizer
      電子情報通信学会超伝導エレクトロニクス研究会 SCE2013-32
    • Place of Presentation
      東北大学 電気通信研究所(仙台)
    • Invited
  • [Presentation] 断熱型超伝導回路と可逆演算への展開

    • Author(s)
      吉川信行
    • Organizer
      応用物理学会超伝導分科会第48回研究会
    • Place of Presentation
      産業技術総合研究所つくばセンター(つくば)
    • Invited
  • [Presentation] SFQ回路を用いたデジタル多重化

    • Author(s)
      吉川信行
    • Organizer
      未踏科学技術協会超伝導科学技術研究会第83回ワークショップ
    • Place of Presentation
      全日通霞が関ビルディング(東京)
    • Invited
  • [Presentation] 断熱型磁束量子パラメトロン回路のためのSplitterセルの設計

    • Author(s)
      (48) 奈良間達也、竹内尚輝、井上健太、山梨裕希、吉川信行
    • Organizer
      第61回応用物理学会春季学術講演会
    • Place of Presentation
      山学院大学相模原キャンパス(神奈川県)
  • [Presentation] 容量性カップリングを用いたCMOS 可逆論理回路の動作実証

    • Author(s)
      井上孔佑、古市真也、吉川信行
    • Organizer
      2014電子情報通信学会総合大会
    • Place of Presentation
      新潟大学五十嵐キャンパス(新潟市)
  • [Presentation] 磁気シールド構造を持つ論理セルを用いた断熱型磁束量子パラメトロン論理回路の設計と測定

    • Author(s)
      井上健太、竹内尚輝、山梨裕希、吉川信行
    • Organizer
      2014電子情報通信学会総合大会
    • Place of Presentation
      新潟大学五十嵐キャンパス(新潟市)
  • [Presentation] SFQ/CMOSハイブリッドメモリ用CMOS SRAMの低消費電力化

    • Author(s)
      佐々木悠太・彭 析竹・西村考正、山梨裕希、吉川信行
    • Organizer
      2014電子情報通信学会総合大会
    • Place of Presentation
      新潟大学五十嵐キャンパス(新潟市)
  • [Presentation] SFQ Digital読み出しのための高感度CMOS増幅器の特性評価

    • Author(s)
      西村考正・佐々木悠太・彭 析竹、山梨裕希、吉川信行
    • Organizer
      2014電子情報通信学会総合大会
    • Place of Presentation
      新潟大学五十嵐キャンパス(新潟市)
  • [Remarks] 「断熱モード単一磁束量子回路の導入によるサブμWマイクロプロセッサの研究」研究紹介

    • URL

      http://www.yoshilab.dnj.ynu.ac.jp/KibanS_HP/

URL: 

Published: 2015-05-28  

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