Principles for the development of a diffusion barrier layer to overcome the process limitations of multi-layer interconnects for semiconductor devices

2014 Fiscal Year Final Research Report

• Project/Area Number: 22226012
• Research Category: Grant-in-Aid for Scientific Research (S)
• Allocation Type: Single-year Grants
• Research Field: Structural/Functional materials
• Research Institution: Tohoku University
• Principal Investigator: KOIKE Junichi 東北大学, 未来科学技術共同研究センター, 教授 (10261588)
• Co-Investigator(Renkei-kenkyūsha): SUTOU Yuji 東北大学, 大学院工学研究科, 准教授 (80375196) ; NEISHI Koji 東北大学, 大学院工学研究科, 助教 (00404020) ; ANDO Daisuke 東北大学, 大学院工学研究科, 助教 (50615820)
• Project Period (FY): 2010-04-01 – 2015-03-31
• Keywords: 銅合金 / 薄膜 / 配線 / 半導体 / 界面 / リフロー / バリア層

Outline of Final Research Achievements

Multilayer interconnection for semiconductors requires the decrease of a barrier layer thickness as thin as possible. This research has focused on the self-formation of the barrier layer and was aimed at understanding the formation mechanism so as to go beyond process limitation with novel materials and processes. The formation mechanism was found to be electric-field induced diffusion. The field strength was dependent on alloying elements, which led to the difference in the formation mechanism. In order to provide solutions to futuristic narrow lines, we developed a chemical vapor deposition method to form an ultrathin barrier layer and a sputter reflow method to fill very narrow lines with copper alloys.

Free Research Field

材料工学