2012 Fiscal Year Final Research Report
Innovative 3D Design for the New Generation Vector Microarchitecture
| Project/Area Number |
22300013
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Tohoku University |
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Principal Investigator |
KOBAYASHI Hiroaki 東北大学, サイバーサイエンスセンター, 教授 (40205480)
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| Co-Investigator(Renkei-kenkyūsha) |
TAKIZAWA Hiroyuki 東北大学, 大学院・情報科学研究科, 准教 授 (70323996)
EGAWA Ryusuke 東北大学, サイバーサイエンスセンター, 助教 (80374990)
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| Project Period (FY) |
2010 – 2012
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| Keywords | 計算機アーキテクチャ / 3次元集積技術 / ベクトルアーキテクチャ |
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| Research Abstract |
This study discusses a new design methodology for a microarchitecture of next-generation, low-power high-performance vector processors by using 3D die-stacking technology. A strategy for mixed design of conventional 2D design and TSV (Through-Silicon-Via)-based 3D design that realizes a good trade-off between them in the all level of on-chip units design has also been proposed. Through the performance evaluation of a prototyped 3D vector processor, the effectiveness of 3D design regarding power consumption and performance has been clarified.
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