Power Adjustment Testing for Next-Generation Low-Power LSI Circuits

2012 Fiscal Year Final Research Report

• Project/Area Number: 22300017
• Research Category: Grant-in-Aid for Scientific Research (B)
• Allocation Type: Single-year Grants
• Section: 一般
• Research Field: Computer system/Network
• Research Institution: Kyushu Institute of Technology
• Principal Investigator: WEN Xiaoqing 九州工業大学, 情報工程学院, 教授 (20250897)
• Co-Investigator(Kenkyū-buntansha): KAJIHARA Seiji 九州工業大学, 情報工学研究院, 教授 (80252592) ; MIYASE Kohei 九州工業大学, 情報工学研究院, 助教 (30452824)
• Project Period (FY): 2010 – 2012
• Keywords: LSIテスト / 低電力テスト / テスト電力調整 / 遅延テスト / 微小遅延故障 / 活性化パス / 高品質化 / 高信頼化

Research Abstract

There are two major problems in LSI testing, namely decreasing test yield due to excessive delay along sensitized paths and decreasing test quality due to inadequate delay along sensitized paths. In this research, a novel scheme has been established, which dynamically adjusts regional power dissipation in the neighborhood of sensitized paths to minimize its impact on test yield and test quality. This scheme of power adjustment testing is expected to contribute to higher test yield and better test quality.

Research Products

• [Journal Article] Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains (2012)
  • Author(s): S. Wu, L. -T. Wang, X. Wen, Z. Jiang, W. -B. Jone, M. S. Hsiao, L. Tan, Y. Zhang, C. -M. Li, and J. -L. Huang
  • Journal Title: ACM Transactions on Design Automation of Electronic Systems Volume: Vol. 17, Issue 4, Article No. 48
  • Peer Reviewed
• [Journal Article] Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of TDF Patterns (2012)
  • Author(s): H. Salmani, W. Zhao, M. Tehranipoor, S. Chacravarty, P. Girard, and X. Wen
  • Journal Title: ASP Journal of Lower Power Electronics Volume: Vol. 8, No. 2 Pages: 248-258
  • Peer Reviewed
• [Journal Article] Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing (2011)
  • Author(s): K. Miyase, K. Noda, H. Ito, K. Hatayama, T. Aikyo, Y. Yamato, H. Furukawa, X. Wen, and S. Kajihara
  • Journal Title: IEICE Trans. Inf. & Syst. Volume: Vol. E94-D, No. 6 Pages: 1216-1226
  • Peer Reviewed
• [Journal Article] A Study of Capture-Safe Test Generation Flow for At-Speed Testing (2010)
  • Author(s): K. Miyase, X. Wen, S. Ka j ihara, Y. Yamato, A. Takashima, H. Furukawa, K. Noda, H. Ito, K. Hatayama, T. Aikyo, and K. K. Saluja
  • Journal Title: IEICE Trans. Inf. & Syst. Volume: Vol. E93-A, No. 7 Pages: 1309-1318
  • Peer Reviewed
• [Presentation] On Guaranteeing Capture Safety in At-Speed Scan Testing With Broadcast-Scan-Based Test Compression (2013)
  • Author(s): K. Enokimoto, X. Wen, K. Miyase, J.-L. Huang, S. Kajihara, and L.-T. Wang
  • Organizer: Proc. 26th Intl. Conf. on VLSI Design
  • Place of Presentation: Pune, India
  • Year and Date: 20130105-10
• [Presentation] Estimation of the Amount of Don' t-Care Bits in Test Vectors (2012)
  • Author(s): K. Miyase, S. Kajihara, and X. Wen
  • Organizer: Proc. IEEE Workshop on RTL and High Level Testing
  • Place of Presentation: Niigata, Japan
  • Year and Date: 20121122-23
• [Presentation] A Transition Isolation Scan Cell Design for Low Shift and Capture Power (2012)
  • Author(s): Y. -T. Lin, J. -L Huang, and X. Wen
  • Organizer: Proc. IEEE Asian Test Symp
  • Place of Presentation: Niigata, Japan
  • Year and Date: 20121119-22
• [Presentation] A Novel Capture-Safety Checking Method for Multi-Clock Designs and Accuracy Evaluation with Delay Capture Circuits (2012)
  • Author(s): K. Miyase, M. Aso, R. Ootsuka, X. Wen, H. Furukawa, Y. Yamato, K, Enokimoto, and S. Kajihara
  • Organizer: Proc. IEEE VLSI Test Symp.
  • Place of Presentation: Hawaii, USA
  • Year and Date: 20120423-26
• [Presentation] A Transition Isolation Scan Cell Design for Low Shift and Capture Power (2012)
  • Author(s): Y. -T. Lin, J. -L. Huang, and X. Wen
  • Organizer: Proc. VLSI Test Technology Workshop
  • Place of Presentation: Yilan, Taiwan
  • Year and Date: 2012-01-10
• [Presentation] Additional Path Delay Fault Detection with Adaptive Test Data (2011)
  • Author(s): K. Miyase, H. Tanaka, K. Enokimoto, X. Wen, and S. Kajihara
  • Organizer: Proc. IEEE Workshop on RTL and High Level Testing
  • Place of Presentation: Jaipur, India
  • Year and Date: 20111125-26
• [Presentation] Effective Launch Power Reduction for Launch-Off-Shift Scheme with Adjacent-Probability-Based X-Filling (2011)
  • Author(s): K. Miyase, U. Uchinodan, K. Enokimoto, Y. Yamato, X. Wen, S. Kajihara, F. Wu, L. Dilillo, A. Bosio, and P. Girard
  • Organizer: Proc. IEEE Asian Test Symp.
  • Place of Presentation: New Delhi, India
  • Year and Date: 20111120-23
• [Presentation] Efficient BDD-based Fault Simulation in Presence of Unknown Values (2011)
  • Author(s): M. A. Kochte, S. Kundu, K. Miyase, X. Wen, and H. -J. Wunderlich
  • Organizer: Proc. IEEE Asian Test Symp.
  • Place of Presentation: New Delhi, India
  • Year and Date: 20111120-23
• [Presentation] Towards the Next Generation of Low-Power Test Technologies (2011)
  • Author(s): X. Wen
  • Organizer: Proc. IEEE Int' 1. Conf. on ASIC
  • Place of Presentation: Hong Kong, China
  • Year and Date: 20111025-28
• [Presentation] Clock-Gating-Aware Low Launch WSA Test Pattern Generation for At-Speed Scan Testing (2011)
  • Author(s): Y. -T. Lin, J. -L. Huang, and X. Wen
  • Organizer: Proc. IEEE Intl. Test Conf.
  • Place of Presentation: Anaheim, USA
  • Year and Date: 20110918-23
• [Presentation] A Novel Scan Segmentation Design Method for Avoiding Shift Timing Failure in Scan Testing (2011)
  • Author(s): Y. Yamato, X. Wen, M. A. Kochte, K. Miyase, S. Ka j ihara, and L. -T. Wang
  • Organizer: Proc. IEEE Intl. Test Conf.
  • Place of Presentation: Anaheim, USA
  • Year and Date: 20110918-23
• [Presentation] SAT-based Capture-Power Reduction for At-Speed Broadcast-Scan-Based Test Compression Architectures (2011)
  • Author(s): M. A. Kochte, K. Miyase, X. Wen, S. Ka j ihara, Y. Yamato, K. Enokimoto, and H.-J. Wunderlich
  • Organizer: Proc. IEEE Intl. Symp. on Low Power Electronics and Design
  • Place of Presentation: Fukuoka, Japan
  • Year and Date: 20110801-03
• [Presentation] Power-Aware Test Generation with Guaranteed Launch Safety for At-Speed Scan Testing (2011)
  • Author(s): X. Wen, K. Enokimoto, K. Miyase, Y. Yamato, M. Kochte, S. Ka j ihara, P. Girard, and M. Tehranipoor
  • Organizer: Proc. IEEE VLSI Test Symp.
  • Place of Presentation: Dana Point, USA
  • Year and Date: 20110501-05
• [Presentation] VLSI Testing and Test Power (2011)
  • Author(s): X. Wen
  • Organizer: Proc. Workshop on Low Power System on Chip (SoC)
  • Place of Presentation: Orlando, USA
  • Year and Date: 2011-07-28
• [Book] Part IV Circuit Testing, Chapter 20: Low-Power Testing for Low-Power LSI Circuits, Advanced Circuits for Emerging Technologies (2012)
  • Author(s): X. Wen and Y. Zorian, John Wiley & Sons
  • Total Pages: 511-528
  • Publisher: New Jersey
• [Remarks]
  • URL: http://aries3a.cse.kyutech.ac.jprwen/