2012 Fiscal Year Final Research Report
Study on architecture of high-performance computers
| Project/Area Number |
22500045
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Nagoya University |
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Principal Investigator |
ANDO Hideki 名古屋大学, 工学研究科, 教授 (40293667)
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| Project Period (FY) |
2010 – 2012
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| Keywords | コンピュータ・アーキテクチャ / メモリ・レベル並列 |
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| Research Abstract |
I studied computer architecture that exploits memory-levelparallelism (MLP) to suppress performance degradation due to slow main memory. MLP is to parallelize memory accesses. I proposed two schemes. One is a virtual reorder buffer scheme that virtually increases the number of instructions a processor supports, and promotes MLP with suppressing cost increase. Another is a dynamic instruction window resizing scheme that enlarges the hardware supporting a large number of instructions, but adaptively resizes the size of the hardware to suppress the adverse effect due to this, i.e., the degradation of the clock speed and difficulty of instruction-level parallelism exploitation. Our evaluation results show that the virtual reorder buffer and the dynamic resizing schemes achieve performance improvement by 35% and 45% over those of the conventional processor, respectively.
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