2012 Fiscal Year Final Research Report
Timing Assured Incremental Physical Design Methods for Next LSI System
| Project/Area Number |
22500049
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Kochi University |
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Principal Investigator |
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| Co-Investigator(Kenkyū-buntansha) |
MICHIAKI Muraoka 高知大学, 教育研究部自然科学系, 教授 (80444777)
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| Project Period (FY) |
2010 – 2012
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| Keywords | 物理設計 / VLSI / タイミング / クロストーク |
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| Research Abstract |
This research aimed at establishment of a new timing performance prediction method and its assured incremental(partial improvement) physical design system for next generation VLSI system. It established two important techniques: one is a proposal of super-high-speed routing method and its verification for high accuracy timing estimation in a few seconds , the other is a cross-talk timing-error-free detailed routing method and its verification.
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Research Products
(17 results)
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[Presentation] A Study of Crosstalk-Free Maze-Router2012
Author(s)
Yoshiya Fujii,Syunsuke Nakai, Michiaki Muraoka,Masahiko Toyonaga
Organizer
The Shikoku-section Joint Convention of the Institutes of Electrical and related Engineers (SJCIEE)
Place of Presentation
Kagawa
Year and Date
2012-09-29
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