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2012 Fiscal Year Final Research Report

Study on intelligent-processing LSI with multi resolutions- and/or layers- cellular automata

Research Project

  • PDF
Project/Area Number 22500115
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeSingle-year Grants
Section一般
Research Field Intelligent informatics
Research InstitutionHokkaido University

Principal Investigator

IKEBE Masayuki  北海道大学, 大学院・情報科学研究科, 准教授 (20374613)

Project Period (FY) 2010 – 2012
Keywordsセルオートマトン / 局所 / 大局 / 画像処理 / 多重解像度 / イメージセンサ
Research Abstract

We developed an efficient CA algorithm for single-image super resolution based on low-memory box filtering. In FPGA implementation, we realize real-time QVGA to VGA movie processing and higher-quality jaggy suppression than bi-cubic interpolation. Moreover we implemented a fast 2-D local histogram equalization method, which with compensates halo effects, without kernel-size dependency. Using a2.9-GHz CPU with our method, the algorithm achieves 2 million pixels per 0.4 sec operation without the need for down sampling, Single Instruction/Multiple Data (SIMD) or multi-thread operation.

  • Research Products

    (7 results)

All 2013 2012 2011 Other

All Journal Article (2 results) (of which Peer Reviewed: 2 results) Presentation (3 results) Patent(Industrial Property Rights) (2 results) (of which Overseas: 1 results)

  • [Journal Article] FPGA Implementation of Single-Image Super Resolution based on Frame-Bufferless Box Filtering2013

    • Author(s)
      Yuki Sanada, Takanori Ohira, Satoshi Chikuda, Masaki Igarashi, Masayuki Ikebe, Tetsuya Asai,and Masato Motomura
    • Journal Title

      Journal of Signal Processing

      Volume: vol.17(in press)

    • Peer Reviewed
  • [Journal Article] Fast bilateral filtering using recursive moving sum2012

    • Author(s)
      M. Igarashi, M. Ikebe, S. Shimoyama, J. Motohisa
    • Journal Title

      Nonlinear Theory and Its Applications, IEICE

      Volume: Vol.3 Pages: 222-232

    • Peer Reviewed
  • [Presentation] A 11B 5.1uW Multi-Slope ADC with a TDC Using Multi-Phase Clock Signals2012

    • Author(s)
      K. Kim, M. Ikebe, J. Motohisa, E. Sano
    • Organizer
      IEEE Int'l Conf. Electronics Circuits and Systems
    • Place of Presentation
      Seville(Spain) HOTEL BARCELO RENACIMIENTO
    • Year and Date
      20121209-12
  • [Presentation] A 0.6-4.5 GHz inductor-less CMOS low noise amplifier with gyrator-C network2011

    • Author(s)
      Kondou, A. Ikebe M Motohisa, J. Amemiya, Y. Sano, E.
    • Organizer
      IEEE Int'l Conf. Electronics Circuits and Systems
    • Place of Presentation
      Beirut(Lebanon) Crown Plaza Hotel
    • Year and Date
      20111211-14
  • [Presentation] A CMOS imager with negative feedback pixel circuits and its applications2011

    • Author(s)
      M.Ikebe and J. Motohisa
    • Organizer
      International Symposium on Photoelectronic Detection and Imaging: Advances in Imaging Detectors and Applications
    • Place of Presentation
      Beijing(China) China NationalConvention Center
    • Year and Date
      20110524-26
  • [Patent(Industrial Property Rights)] 積分型AD変換装置およびCMOSイメージセンサ

    • Inventor(s)
      池辺将之
    • Industrial Property Rights Holder
      北海道大学
    • Industrial Property Number
      特願2012-33196
  • [Patent(Industrial Property Rights)] アクティブコモンモードフィルタ

    • Inventor(s)
      池辺将之、近藤亮
    • Industrial Property Rights Holder
      北海道大学
    • Industrial Property Number
      PCT/JP2012/067976
    • Overseas

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Published: 2014-08-29  

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