2012 Fiscal Year Final Research Report
Robustness against delay variations and design optimization for datapath circuits with post silicon timing tuning mechanism
| Project/Area Number |
22560326
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | Japan Advanced Institute of Science and Technology |
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Principal Investigator |
KANEKO Mineo 北陸先端科学技術大学院大学, 情報科学研究科, 教授 (00185935)
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| Project Period (FY) |
2010 – 2012
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| Keywords | 集積回路 / 製造ばらつき / セットアップ・ホールド / タイミング・スキュー / 高位合成 / タイミングテスト / 資源割り当て / PDE調整 |
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| Research Abstract |
LSIs suffers variations during fabrication process, and timing fault due to those variations is one of the biggest problems for current and future advanced LSIs. Timing skew tuning after fabrication (Post Silicon Skew Tuning) is a key technology to overcome such timing problem and to draw the best possible performance of individual chip. Register transfer level design optimizations of LSIs with PSST mechanism and skew tuning algorithms together with optimized timing test schedule have been developed in this project.
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