2012 Fiscal Year Final Research Report
Automatic Mapping Architecture for Ultra Low Power Many-coreProcessor
| Project/Area Number |
22700053
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
Computer system/Network
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| Research Institution | The University of Tokyo (2012)
Nara Institute of Science and Technology (2010-2011) |
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Principal Investigator |
NAKADA Takashi 東京大学, 大学院・情報理工学系研究科, 特任助教 (00452524)
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| Project Period (FY) |
2010 – 2012
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| Keywords | 計算機アーキテクチャ / 計算機システム / 省エネルギー |
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| Research Abstract |
Automatic mapping architecture has been proposed. It enables us to use existing programs on linear array processors, which can achieve high performance with limited data supply throughput. A tradeoff between performance and hardware cost is explored. Additionally, time division execution and fault tolerant mechanisms are proposed and their feasibility is evaluated. We have confirmed that wider range of application for linear array processors.
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