2022 Fiscal Year Research-status Report
A HW-SW design and execution platform for sustainable edge-computing devices based on HDLRuby
| Project/Area Number |
22K11965
|
|---|
| Research Institution | Ariake National College of Technology |
|---|
Principal Investigator |
Gauthier Lovic 有明工業高等専門学校, 創造工学科, 教授 (90535717)
|
|---|
| Co-Investigator(Kenkyū-buntansha) |
石川 洋平 有明工業高等専門学校, 創造工学科, 准教授 (50435476)
|
|---|
| Project Period (FY) |
2022-04-01 – 2027-03-31
|
| Keywords | HDL / RTL simulation / HW/SW Co-Design |
|---|
| Outline of Annual Research Achievements |
The research aims to provide a design flow for digital devices based on the HDLRuby hardware description language, focusing on design productivity and seamless hardware/software integration. During the year, the implementation of an efficient register transfer level (RTL) simulator for HDLRuby has been explored leading to the proposal of a hybrid solution whose performance surpasses the popular simulator Icarus Verilog (1). A full evaluation of the efficiency of HDLRuby for describing complex hardware using high-level software paradigms like object-oriented programming and genericity has also been done for several edge-computing applications including convolutional neural networks (2). In the evaluation, the design time, the file sizes, the hardware synthesis time, and the efficiency of the resulting hardware have been considered for comparing the HDLRuby flow with a standard Verilog HDL one. The results showed that for resulting hardware with identical performance, the design time with HDLRuby was faster, a much more scalable. Both works lead to the following publications:
(1) Implementation and Comparison of Several Register Transfer Level Simulation Engines for the HDLRuby Language (ICIAE 2023)
(2) HDLRuby: A Ruby Extension for Hardware Description and its Translation to Synthesizable Verilog HDL (ACM TECS 2023)
|
| Current Status of Research Progress |
Current Status of Research Progress
2: Research has progressed on the whole more than it was originally planned.
Reason
The first year has been dedicated to setting up the grounds for hardware/software integration, with the evaluation of using high-level software paradigms for describing hardware and with the design and optimization of an HDLRuby simulator that will serve as a backbone for hardware-software co-simulation. Currently, a library for describing hardware with software-like code and a software processor for directly executing software is being designed.
Hence the global progression is as planned. In detail though, the design part is more advanced than expected whereas the survey of edge-computing part is less. It is planned to progress more on the latter this year.
|
| Strategy for Future Research Activity |
Now that it has been shown that software high-level paradigms can be successfully been applied or hardware description, we plan to integrate software code within HDLRuby. For that purpose, we are currently designing a new library for HDLRuby for describing hardware using software algorithms without requiring any high-level synthesis (a), and a lightweight soft processor for executing directly Ruby or C code that will serve as a runtime for software applications (b). In parallel, libraries of components that can be seamlessly been switched from hardware to software must also be designed.
For the academic side, publications about (a) and (b) are planned for this next year.
We also have some partnerships with the industry planned for prototyping the design of chips with HDLRuby.
|
| Causes of Carryover |
The paper entitled "HDLRuby: A Ruby Extension for Hardware Description and its Translation to Synthesizable Verilog HDL" published this year requires a significant extra fee for being set to open access. This fee could only be paid before the fiscal year completes due to delays in the procedure.
|
