A Study on Acceleration by Temporal Blocking for Real-world Applications

2023 Fiscal Year Final Research Report

• Project/Area Number: 22K17898
• Research Category: Grant-in-Aid for Early-Career Scientists
• Allocation Type: Multi-year Fund
• Review Section: Basic Section 60090:High performance computing-related
• Research Institution: Nagoya University
• Principal Investigator: Hoshino Tetsuya 名古屋大学, 情報基盤センター, 准教授 (40775946)
• Project Period (FY): 2022-04-01 – 2024-03-31
• Keywords: 高性能計算 / ステンシル計算 / 時空間ブロッキング / 自動チューニング

Outline of Final Research Achievements

The specific calculation pattern for a discrete grid in time and space that arises when solving differential equations analytically is called a stencil calculation, and it is an important kernel that frequently appears in various fluid simulations. Acceleration of stencil calculations has been studied extensively, and the temporal blocking method is one such method, but has rarely been applied to real applications because it requires very complicated programming. Furthermore, since the performance of temporal blocking is highly dependent on the performance parameters of the processor executing the blocking, it is not realistic to optimize the blocking manually. Therefore, in this study, the performance modeling required for auto-tuning of temporal blocking was performed using state-of-the-art CPUs.

Free Research Field

高性能計算

Academic Significance and Societal Importance of the Research Achievements

本研究では、主にHigh Bandwidth Memory（HBM）を搭載した最新のCPUである、富岳スパコンのA64FXや、Intel Xeon Sapphire Rapids世代のCPUを用いて、性能モデル化を進めた点に大きな価値がある。時空間ブロッキング手法はその性質上、特にメインメモリの性能とラストレベルキャッシュの性能比に性能が大きく依存する。この性能比はHBMの登場によって既存のCPUと大きく変化し、本研究では性能モデルによってその影響を明らかにしたことが、高性能計算分野において意義のある成果である。また当初想定していなかった、命令レイテンシの影響を明らかにした点も意義がある。