2022 Fiscal Year Research-status Report
Event-Clock Hybrid Driven Reconfigurable Perception-Computation Technology
| Project/Area Number |
22K21280
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| Research Institution | Nara Institute of Science and Technology |
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Principal Investigator |
KAN YIRONG 奈良先端科学技術大学院大学, 先端科学技術研究科, 助教 (50963732)
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| Project Period (FY) |
2022-08-31 – 2024-03-31
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| Keywords | Reconfigurable Computing / CGRA / Neuromorphic Systems / Spiking Neural Networks |
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| Outline of Annual Research Achievements |
This year, we developed and verified the following technologies for the hybrid-driven reconfigurable perception-computation platform: (1) Spike coding of Electroencephalogram (EEG) signals and its spiking neural network (SNN)-based processing. In several works, we successfully applied spike coding to adaptive, stochastic and frequency coding of EEG signals, respectively, and achieved competitive sleep stage classification accuracy based on SNN; (2) A ternary weight quantization method for deep SNNs and hardware implementation. In this work, we achieved energy-efficient inference hardware by quantizing the weights of SNNs to {-1, 0, 1}. The gradient disappearance problem during model training is avoided by designing cross-layer connections. Simple logical operations can be used in ternary weights SNNs at the inference stage, to reducing hardware overhead; (3) Training and construction mechanism of reconfigurable bisection neural network (BNN) topology. We proposed a general construction method of BNN and its training mechanism. By constructing a mask matrix with a bisection structure, we can automatically train a BNN model with a specific topology.
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| Current Status of Research Progress |
Current Status of Research Progress
2: Research has progressed on the whole more than it was originally planned.
Reason
Current research progress matches expectations. The main reasons are: (1) spike coding works well on time series data (such as EEG signals); (2) We already have a foundation in the efficient hardware implementation of SNNs; (3) Completed the theoretical basis of reconfigurable NNs. 3 papers have been published in international journals; 4 papers have been published in international conferences; and currently 2 papers are being submitted to international conferences.
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| Strategy for Future Research Activity |
Firstly, we will integrate SNN with bisection topology to realize reconfigurable SNN hardware. Then, the adders and multipliers in the original SNN hardware are replaced with look-up tables to realize low-power calculations. Secondly, we will explore the integration of stochastic computing and BNN to realize a computing architecture with temporal-spatial re-configurability. Finally, we apply the proposed platform to various online perception/computation applications.
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| Causes of Carryover |
We need time to work on the VLSI design, so the chips will be produced in a combined current and next year's funding.
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