2013 Fiscal Year Final Research Report
Research on Cirsuit Topologies for Noise Reduction in Power Electronics Circuits
| Project/Area Number |
23360126
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Power engineering/Power conversion/Electric machinery
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| Research Institution | Kyushu University |
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Principal Investigator |
SHOYAMA Masahito 九州大学, システム情報科学研究科(研究院, 教授 (40187513)
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| Project Period (FY) |
2011-04-01 – 2014-03-31
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| Keywords | スイッチングノイズ / 三相インバータ / ブリッジレスPFC / パワーコンディショナ / コモンモードノイズ電流 / ノイズ電流相殺 / 寄生要素 |
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| Research Abstract |
Power electronic circuits are widely expanding as energy-saving key technologies, however, a switching noise is generated because a switching element may repeat an on/off action at high frequency. Conventional methods to reduce a noise are post-installed noise filters, snubber elements, etc. in the main circuit, which lead to the increase in size or weight and the cost rise, and the methods had taken great time to it. This research is to reduce noise by means of the new circuit topology in a power electronics main circuit. The method of reducing the common-mode-noise current due to the parasitic capacitance of the semiconductor switch of a three phase inverter circuit and the internal parasitic capacitance in a motor and the noise reduction method in a totem pole type bridgeless power factor correction converter are described.
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