2013 Fiscal Year Final Research Report
High Performance, Low Power Hetero-CMOS Device using Compound Si Wafer
| Project/Area Number |
23360146
|
|---|
| Research Category |
Grant-in-Aid for Scientific Research (B)
|
| Allocation Type | Single-year Grants |
|---|
| Section | 一般 |
|---|
| Research Field |
Electron device/Electronic equipment
|
|---|
| Research Institution | Tohoku University |
|---|
Principal Investigator |
LEE KANGWOOK 東北大学, 未来科学技術共同研究センター, 教授 (90534503)
|
|---|
| Co-Investigator(Kenkyū-buntansha) |
FUKUSHIMA Takafumi 東北大学, 未来科学技術共同研究センター, 准教授 (10374969)
TANAKA Tetsu 東北大学, 大学院・医工学研究科, 教授 (40417382)
BEA Jichel 東北大学, 未来科学技術共同研究センター, 助教 (40509874)
MURUGESAN Mariappan 東北大学, 未来科学技術共同研究センター, 産学官連携研究員 (10509699)
|
|---|
| Co-Investigator(Renkei-kenkyūsha) |
KOYANAGI Mitsumasa 東北大学, 未来科学技術共同研究センター, 教授 (60205531)
|
|---|
| Project Period (FY) |
2011-04-01 – 2014-03-31
|
| Keywords | 複合Siウェハ / ヘテロＣＭＯＳトランジスタ / セルフアセンブリー張り合わせ |
|---|
| Research Abstract |
We developed new technology for high-performance, low-power hetero-junction CMOS comprising InGaAs NMOS and Ge PMOS on a large-dia. Si wafer. Ge chips and InGaAs chips are precisely (<1um accuracy) and tightly bonded (20MPa) on a smooth surface roughness (Ra 0.5 angstrom) of P-TEOS hydrophilic area on a Si wafer by using self-assembly technology. Shallow p-n junction technologies of ion implantation and annealing condition for hetero-junction CMOS are established. We successfully implemented Ge and InGaAs photodiodes on a Si wafer by using these technologies. This study shows the opportunity to manufacture high-performance, low-power Ge/InGaAs hetero-junction CMOS device on an 8/12 inch Si wafer with low cost.
|
