2013 Fiscal Year Final Research Report
A method of high-level synthesis for multi-cycle transient fault tolerant digital systems
| Project/Area Number |
23500065
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Multi-year Fund |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Hiroshima City University |
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Principal Investigator |
INOUE Tomoo 広島市立大学, 情報科学研究科, 教授 (40252829)
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| Project Period (FY) |
2011 – 2013
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| Keywords | ソフトエラー / 高位合成/動作合成 / 過渡故障 / 信頼性 / 3重系/TMR / 誤り訂正・誤り検出 / 耐故障設計 |
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| Research Abstract |
As the advance in semiconductor technologies, transient faults caused by particle strike have become a matter of concern, and further it is predicted that such faults can span across more than one clock cycle.
We proposes a high-level synthesis algorithm for long duration transient fault tolerance. On the basis of the properties of operational units for transient error correction and detection among operations, we present (1) a force-directed scheduling algorithm with the force derived from the estimation of operational units according to the properties of error correction and detection, (2) a binding algorithm aiming at achieving both of correctablility and detectability with minimizing the number of operational units, and (3) a method for synthesizing transient fault tolerant controllers that utilizes the correctability/detectability of datapaths. The proposed algorithm can derive multi-cycle fault tolerant systems with small hardware resources compared with simply-tripled datapaths.
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