2013 Fiscal Year Final Research Report
Efficient Hardware Algorithms for Solving Combinatorial Optimization Problems by Using FPGAs with Dynamic Partial Reconfiguration
| Project/Area Number |
23500066
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Multi-year Fund |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Hiroshima City University |
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Principal Investigator |
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| Co-Investigator(Renkei-kenkyūsha) |
NAGAYAMA Shinobu 広島市立大学, 大学院・情報科学研究科, 准教授 (10405491)
INAGI Masato 広島市立大学, 大学院・情報科学研究科, 助教 (50468302)
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| Project Period (FY) |
2011 – 2013
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| Keywords | FPGA / 動的部分再構成 / 組合せ最適化 / ネットワーク侵入検知 |
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| Research Abstract |
In this research, we proposed several hardware algorithms to solve combinatorial optimization problems. First, we proposed a hardware algorithm to solve the maximum clique problem of large graphs by producing a set of small subgraphs, and show its implementation results using a dynamically partially reconfigurable FPGA. Second, we proposed a new hardware satisfiability solver, which is based on the bottom-up solver proposed in our previous study. It can obtain a solution for a large instance of the problem. Third, we proposed a regular expression matching (REM) hardware engine. In the proposed method, the circuit size is reduced keeping the advantages that any RE can be handled and a pattern can be updated immediately.
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