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2013 Fiscal Year Final Research Report

A Study of a Tile-based NoC System using IPs and its Design

Research Project

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Project/Area Number 23500069
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeMulti-year Fund
Section一般
Research Field Computer system/Network
Research InstitutionWaseda University

Principal Investigator

WATANABE TAKAHIRO  早稲田大学, 理工学術院, 教授 (70230969)

Project Period (FY) 2011 – 2013
KeywordsNoC / SoC / IP / アーキテクチャ / 低電力 / ルーティング / PCB / 自動配線アルゴリズム
Research Abstract

NoC(Network on Chip) is one of a promising solution to implement the ultra large scale system with high performance on a chip. For improving the design efficiency of NoC, an IP-reused design method was proposed to implement a core in each tile, where design techniques for instruction-level customizable processor IP were developed and its design environment was constructed. Application-specific NoCs of Two- or Three-dimension were also discussed, and NoC architectures for high throughput, low latency and low power were explored and routing algorithms with high performance or fault-tolerancy were developed. Besides, to solve a signal-delay problem of the board-level system composed of NoCs and SoCs(System on Chip), several routing algorithm ware proposed and evaluated.

  • Research Products

    (21 results)

All 2014 2013 2012 2011 Other

All Journal Article (10 results) (of which Peer Reviewed: 10 results) Presentation (10 results) Remarks (1 results)

  • [Journal Article] LVSの出力情報を活用した VLSI 電源配線幅の高速検証システム2013

    • Author(s)
      亀井智紀, 渡邊孝博, 川北真裕
    • Journal Title

      電子情報通信学会論文誌D

      Volume: Vol.J96-D, No.5 Pages: 1330-1337

    • Peer Reviewed
  • [Journal Article] An Efficient Algorithm for 3D NoC Architecture Optimization2013

    • Author(s)
      Xin Jiang, Ran Zhang and Takahiro Watanabe
    • Journal Title

      IPSJ Trans. System LSI Design Methodology (情報処理学会)

      Volume: 6 Pages: 34-41

    • Peer Reviewed
  • [Journal Article] Region-oriented Placement Algorithm for Coarse-grained Power-gating FPGA Architecture2012

    • Author(s)
      C.Li, Y.Dong and T.Watanabe
    • Journal Title

      IEICE Trans Information and Systems

      Volume: E95-D, 2 Pages: 314-323

    • Peer Reviewed
  • [Journal Article] A New Recovery Mechanism in Superscalar Microprocessors by Recovering Critical Misprediction2011

    • Author(s)
      Jiongyao Ye, Yu Wan and Takahiro Watanabe
    • Journal Title

      IEICE Trans. Fundamentals of Electoronics, Communications and Computer Sciences

      Volume: E94-A, 12 Pages: 2639-2648

    • Peer Reviewed
  • [Journal Article] A Hybrid Layer- Multiplexing and Pipeline Architecture for Efficient FPGA-based Multilayer Neural Network2011

    • Author(s)
      Y.P.Dong, C.Li, Z.Lin and Takahiro Watanabe
    • Journal Title

      IEICE NOLTA

      Volume: E94-N, 10 Pages: 522-532

    • Peer Reviewed
  • [Journal Article] An Adaptive Various-width Data Cache for Low Power Design2011

    • Author(s)
      Jiongyao Ye, Yu Wan, Takahiro Watanabe
    • Journal Title

      IEICE

      Volume: E94-D Pages: 1539-1546

    • Peer Reviewed
  • [Journal Article] Analysis Before Starting an Access : A New Power-Efficient Instruction Fetch Mechanism2011

    • Author(s)
      Jiongyao Ye, Yingtao Hu, Takahiro Watanabe
    • Journal Title

      IEICE

      Volume: E94-D 7 Pages: 1398-1408

    • Peer Reviewed
  • [Journal Article] A Sophisticated Routing Algorithm in 3D NoC with Fixed TSVs for Low Energy and Latency

    • Author(s)
      Xin Jiang, Lian Zeng, Takahiro Watanabe
    • Journal Title

      IPSJ Trans.SLDM

      Volume: vol.13 (to appear)

    • Peer Reviewed
  • [Journal Article] Region Oriented Routing FPGA Architecture for Dynamic Power Gating

    • Author(s)
      Ce Li , Yiping Dong and Takahiro Watanabe
    • Journal Title

      IEICE Trans.Fudamentals

      Volume: vol.E95-A 12 Pages: 2199-2207

    • DOI

      10.1587/transfun.E95.A

    • Peer Reviewed
  • [Journal Article] Low Power Placement and Routing for the Coarse-Grained Power Gating FPGA Architecture

    • Author(s)
      C. Li, Y.P.Dong and T.Watanabe
    • Journal Title

      IEICE Trans. Fundamentals of Electronics Communications and Computer Sciences

      Volume: E94-A, 12 Pages: 2519-2527

    • Peer Reviewed
  • [Presentation] Efficient Delay-matching Bus Routing by using Multi-layers2014

    • Author(s)
      Yang Tian, Ran Zhang, Takahiro Watanabe
    • Organizer
      Int. Conf. on Electronics Packaging
    • Place of Presentation
      Toyama
    • Year and Date
      20140400
  • [Presentation] Flexible L1 Cache Optimization for a Low Power Embedded System2013

    • Author(s)
      Huatao ZHAO, Sijie YIN, Yuxin Sun, Takahiro WATANABE
    • Organizer
      2013 Int .Conf. Mechatronic Sciences, Electric Engineering and Computer
    • Place of Presentation
      Niiata
    • Year and Date
      20131200
  • [Presentation] Adaptive Router with Predictor using Congestion Degree for 3D Network-on-Chip2013

    • Author(s)
      Lian Zeng, Xin Jiang, Takahiro Watanabe
    • Organizer
      Proc. 2013 Int. Soc Design Conf. (ISOCC)
    • Place of Presentation
      Busan
    • Year and Date
      20131100
  • [Presentation] A Sorting-Based IO Connection Assignment for Flip-Chip Designs2013

    • Author(s)
      Ran Zhang, Xue Wei, Takahiro Watanabe
    • Organizer
      the 10th Int. Conf. ASIC (ASICON 2013)
    • Place of Presentation
      Shenzhen
    • Year and Date
      20131000
  • [Presentation] Pseudo Dual Path Processing to Reduce the Branch Misprediction Penalty in Embedded Processors2013

    • Author(s)
      Huatao ZHAO, Jiongyao YE, Yuxin Sun, Takahiro WATANABE
    • Organizer
      The 10th Int. Conf. on ASIC
    • Place of Presentation
      Shenzhen
    • Year and Date
      20131000
  • [Presentation] A Parallel Routing Method for Fixed Pins using Virtual Boundary2013

    • Author(s)
      Ran Zhang, Takahiro Watanabe
    • Organizer
      Proc. IEEE 2013 TENCON-Spring
    • Place of Presentation
      Sydney
    • Year and Date
      20130400
  • [Presentation] An Efficient Design Algorithm for Exploring Flexible Topologies in Custom Adaptive 3D NoCs for High Performance and Low Power2011

    • Author(s)
      Xin Jiang, Ran Zhang and Takahiro Watanabe
    • Organizer
      Proc. 2011 IEEE 9th Int.Conf.on ASIC (ASICON 2011)
    • Place of Presentation
      Beijin
    • Year and Date
      20111100
  • [Presentation] New Power-aware Placement for Region based FPGA Architecture combined with Dynamic Power Gating by PCHM2011

    • Author(s)
      C.Li, Y.P.Dong and T. Watanabe
    • Organizer
      Proc.ISLPED'11 (Int'l Symp. Low Power Electronics Design)
    • Place of Presentation
      Fukuoka
    • Year and Date
      20110800
  • [Presentation] New Power Efficient FPGA Design Combining with Region-Constrained Placement and Multiple Power Domains2011

    • Author(s)
      C. Li, Y.P. Dong, Takahiro Watanabe
    • Organizer
      Proc.IEEE NEWCAS'11 (IEEE 9th Int. Conf. New Circuits and Systems)
    • Place of Presentation
      Paris
    • Year and Date
      20110600
  • [Presentation] A High Performance Digital Neural Processor Design by Network on Chip Architecture2011

    • Author(s)
      Y.Dong, Y.Li and Takahiro Watanabe
    • Organizer
      Proc. VLSI-DAT'11
    • Place of Presentation
      Hsinchu
    • Year and Date
      20110500
  • [Remarks] ホームページ

    • URL

      http://www.f.waseda.jp/watt/homepage/index_en.html

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Published: 2015-07-16  

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