2013 Fiscal Year Final Research Report
Development and Application of Multi-scale Simulation System for the Fabrication of Through Silicon Via
| Project/Area Number |
23560067
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Multi-year Fund |
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| Section | 一般 |
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| Research Field |
Engineering fundamentals
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| Research Institution | Kyoto University |
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Principal Investigator |
KANEKO Yutaka 京都大学, 情報学研究科, 助教 (00169583)
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| Project Period (FY) |
2011 – 2013
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| Keywords | シリコン貫通電極 / 動的モンテカルロ法 / 空孔 / 添加剤 / パルスめっき |
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| Research Abstract |
Through silicon via (TSV) is a promising technique to realize short connects among the stacked chips in three dimensional packaging in microelectronics, which would reduce signal delays to allow high-density and high-speed performance. The crucial point in TSV technology is to fill high aspect ratio via holes without creating voids. In this work we studied the optimal conditions for TSV filling by using kinetic Monte Carlo simulation. In copper electrodeposition, four kinds of additives are included. We have performed a series of simulations for various deposition conditions by changing additive concentrations and current patterns. We found optimal conditions of additive concentrations and current patterns, and obtained a lot of results on the mechanism of TSV filling. These results corresponds to experiments and are expected to contribute to TSV technology.
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