Improvement of power efficiency and performance of super parallel processors by application of data compression technology

2014 Fiscal Year Final Research Report

• Project/Area Number: 23700052
• Research Category: Grant-in-Aid for Young Scientists (B)
• Allocation Type: Multi-year Fund
• Research Field: Computer system/Network
• Research Institution: Tokyo Institute of Technology
• Principal Investigator: KANEKO Haruhiko 東京工業大学, 情報理工学(系)研究科, 准教授 (70392868)
• Project Period (FY): 2011-04-28 – 2015-03-31
• Keywords: データ圧縮 / キャッシュメモリ / 並列プロセッサ / キャッシュミス率 / GPU

Outline of Final Research Achievements

We proposed a low-latency and high-throughput lossless compression algorithm, named periodic pattern coding, to improve the memory access performance of super parallel processors. Compression ratio of the proposed method is evaluated by a GPU simulator, and result showed that the proposed method has higher compression ratio compared to conventional compression methods. Also, evaluations of the cache miss ratio and instructions per cycle (IPC) demonstrated that the proposed method is effective to improve the processor performance. Compression/decompression circuits are designed using hardware description language, and results showed that the circuit provides high processing throughputs.

Free Research Field

データ圧縮