2013 Fiscal Year Final Research Report
A High-Performance High-Reliable Architecture for Better Energy Efficiency and Wear-out Toleration
| Project/Area Number |
23700060
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Multi-year Fund |
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| Research Field |
Computer system/Network
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| Research Institution | Nara Institute of Science and Technology |
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Principal Investigator |
YAO JUN 奈良先端科学技術大学院大学, 情報科学研究科, 准教授 (40567153)
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| Project Period (FY) |
2011 – 2013
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| Keywords | ディペンダブルコンピューティング |
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| Research Abstract |
To tolerate the increasing electronic error, the traditional way in microprocessor is to use dual or triple modular redundancy for high-dependable execution, which does not show good energy efficiency. In this research, targeting at a low-power high-performance fault toleration, the following points have been carried out: 1. A fusion of temporal and spatial redundancy: 2. A non-TMR based scheme to locate the permanent failure; (3) Architectural method to aid NBTI effects. The results of this research have been published in 7 journal papers and 9 international conference papers with referee.
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