2013 Fiscal Year Final Research Report
A Study of Acceleration Technique for Many-core Architecture Simulation Considering Global Program Structure
| Project/Area Number |
23700064
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Multi-year Fund |
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| Research Field |
Computer system/Network
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| Research Institution | Waseda University |
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Principal Investigator |
KIMURA Keiji 早稲田大学, 理工学術院, 教授 (50318771)
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| Project Period (FY) |
2011 – 2013
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| Keywords | コンピュータアーキテクチャ / マルチコア / メニーコア / アーキテクチャシミュレーション / 並列化アプリケーション |
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| Research Abstract |
A fast and high accuracy architecture simulation technique for multi-core and many-core processors are proposed in this study. By this proposed technique, an architecture simulator changes its precision and simulation speed appropriately under the assumption that a parallelized application is executed on a multi-core or a many-core.
The evaluation results with four applications each of which has different characteristics show the 16-core multicore simulation gives 443 times speedup within 0.52% error in maximum, and 218 times speedup within 2.75% error on average.
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