Logic verification and synthesis based on difference analysis

2014 Fiscal Year Final Research Report

• Project/Area Number: 24300015
• Research Category: Grant-in-Aid for Scientific Research (B)
• Allocation Type: Partial Multi-year Fund
• Section: 一般
• Research Field: Computer system/Network
• Research Institution: The University of Tokyo
• Principal Investigator: FUJITA Masahiro 東京大学, 大規模集積システム設計教育研究センター, 教授 (70323524)
• Co-Investigator(Kenkyū-buntansha): MATSUMOTO Takeshi 東京大学, 大規模集積システム設計教育研究センター, 助教 (40536140)
• Project Period (FY): 2012-04-01 – 2015-03-31
• Keywords: 形式的解析 / 設計自動合成 / 設計デバッグ / 差異抽出 / 論理関数解析 / プログラム解析

Outline of Final Research Achievements

When developing new hardware/software, it is essential to utilize existing designs efficiently and correctly. We have developed new methods which define and analyze the difference between old and new designs as transformations on sub-circuits and sub-programs. With the proposed methods, users can specify how much modifications/additions are allowed on the old designs in order to meet new specifications. Appropriate transformations are automatically identified with very small numbers of test patterns. With joint efforts with industry, practical usefulness of the proposed methods have been shown by applying them to the real server machines designs. Moreover, the proposed methods can be used as automatic test patterns generation methods for various types of multiple faults or bugs in the design, and for the first time, complete sets of test patterns for multiple faults have successfully been generated on the circuits having more than 10,000 gates.

Free Research Field

ハードウェア・ソフトウェア自動設計技術