Research on high-performance and highly-dependable floating-point arithmetic unit arrays by contriving data representation

2014 Fiscal Year Final Research Report

• Project/Area Number: 24300019
• Research Category: Grant-in-Aid for Scientific Research (B)
• Allocation Type: Partial Multi-year Fund
• Section: 一般
• Research Field: Computer system/Network
• Research Institution: Kyoto University
• Principal Investigator: TAKAGI Naofumi 京都大学, 情報学研究科, 教授 (10171422)
• Co-Investigator(Kenkyū-buntansha): TAKAGI Kazuyoshi 京都大学, 大学院情報学研究科, 准教授 (70273844)
• Project Period (FY): 2012-04-01 – 2015-03-31
• Keywords: 算術演算回路 / 演算器アレイ / オンライン誤り検出

Outline of Final Research Achievements

We have studied methods for making a floating-point arithmetic unit (FPU) array high-performance and highly-dependable by contriving data representation in it. We have proposed methods for constructing concurrently error-detectable FPUs by parity prediction or partial duplication or residue checking, and a method for performing quasi-quadruple precision arithmetic by coupling two double precision floating-point fused multiply-adders. We also proposed a synthesis method of an array of processing elements consisting of an FPU and memory from a program comprising multiple loop structure and matrix operations. In addition, we have developed a simulator of an FPU array.

Free Research Field

計算機科学